- 05 Feb, 2019 1 commit
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Varun Wadekar authored
This patch initilises the per-CPU GIC bits during cold boot and secondary CPU power up. Commit 80c50eea accidentally left out this part. Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 31 Jan, 2019 13 commits
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Varun Wadekar authored
Platforms that do not support bpmp firmware, do not need access to the PMC block from outside of the CPU complex. The agents running on the CPU can always access the PMC through the EL3 exception space. This patch restricts non-secure world access to the PMC block on such platforms. Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch toggles the ring oscillator state across cluster idle as DFLL loses its state. We dont want garbage values being written to the pmic when we enter cluster idle state, so enable "open loop" when we enter CC6 and restore the state to "closed loop" on exit. Change-Id: I56f4649f57bcc651d6c415a6dcdc978e9444c97b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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kalyani chidambaram authored
This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw. Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305 Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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Varun Wadekar authored
The BPMP firmware takes some time to initialise its state on exiting System Suspend state. The CPU needs to synchronize with the BPMP during this process to avoid any race conditions. This patch suspends and resumes the BPMP interface across a System Suspend cycle, to fix this race. Change-Id: I82a61d12ef3eee267bdd8d4386bed23397fbfd2d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch skips past the signature header added to the sc7entry-fw binary by the previous level bootloader. Currently, the size of the header is 1KB, so adjust the start address and the binary size at the time of copy. Change-Id: Id0494548009749035846d54df417a960c640c8f9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch uses the sc7entry-fw base/size values to calculate the TZDRAM fence, so as to move sc7entry-fw inside the TZDRAM fence. Change-Id: I91aeeeece857076c478cdc4c18a6ad70dc265031 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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kalyani chidambaram authored
This patch adds SiP handler for Tegra210 platforms to service read/write requests for PMC block. None of the secure registers are accessible to the NS world though. Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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Varun Wadekar authored
This patch puts all the DMA masters in reset before starting the System Suspend sequence. This helps us make sure that there are no rogue agents in the system trying to over-write the SC7 Entry Firmware with their own. Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw. The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence. The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob. To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend. Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes support for powering down a CPU cluster on Tegra210 platforms as none of them actually use it. Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to enter/exit to/from cluster idle power state on Tegra210 platforms that do not load BPMP firmware. The CPU initates the cluster idle sequence on the last standing CPU, by following these steps: Entry ----- * stop other CPUs from waking up * program the PWM pinmux to tristate for OVR PMIC * program the flow controller to enter CC6 state * skip L1 $ flush during cluster power down, as L2 $ is inclusive of L1 $ on Cortex-A57 CPUs Exit ---- * program the PWM pinmux to un-tristate for OVR PMIC * allow other CPUs to wake up This patch also makes sure that cluster idle state entry is not enabled until CL-DVFS is ready. Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the watchdog timer's interrupt as an FIQ interrupt to the CPU. The interrupt generated by the watchdog is connected to the flow controller for power management reasons, and needs to be routed to the GICD for it to reach the CPU. Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to handle secure PPIs for Tegra watchdog timers. This functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING configuration variable and is only enabled for Tegra210 platforms, for now. Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Jan, 2019 2 commits
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Varun Wadekar authored
This patch includes the console driver from individual platform makefiles and removes it from tegra_common.mk. This allows future platforms to include consoles of their choice. Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch returns error if BPMP initialization fails. The platform code marks the cluster as "runnning" since we wont be able to get it into the low power state without BPMP. Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 18 Jan, 2019 8 commits
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Samuel Payne authored
If ECID is valid, we can use force instantiation otherwise, we should use reseed for random data generation for RNG operations in SE context save DNI because we are not keeping software save sequence in main. Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3 Signed-off-by: Samuel Payne <spayne@nvidia.com>
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Marvin Hsu authored
This change ports the software based SE context save routines. The software implements the context save sequence for SE/SE2 and PKA1. The context save routine is intended to be invoked from the ATF SC7 entry. Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807 Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
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Varun Wadekar authored
This patch increases the MAX_MMAP_REGIONS build flag to allow Tegra210 platforms to dynamically map multiple memory apertures at the same time. This takes care of scenarios when we get multiple requests to memmap memory apertures at the same time. Change-Id: If4fe23b454e7d588e35acfbf024b9ccbb3daccc7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
MISRA Rule 10.3, the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The essential type of a enum member is anonymous enum, the enum member should be casted to the right type when using it. Both UL and ULL suffix equal to uint64_t constant in compiler aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix in platform code. So in some case, cast a constant to uint32_t is necessary. Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Harvey Hsieh authored
This patch saves the TZSRAM context and takes the SoC into System Suspend from the "_wfi" handler. This helps us save the entire CPU context from the TZSRAM, before entering System Suspend. In the previous implementation we missed saving some part of the state machine context leading to an assert on System Suspend exit. Change-Id: I4895a8b4a5e3c3e983c245746ea388e42da8229c Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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Samuel Payne authored
This patch enables clocks to the SE and Entropy block and gets them out of reset, before starting the context save operation. Change-Id: Ic196be8fb833dfd04c0e8d460c07058429999613 Signed-off-by: Samuel Payne <spayne@nvidia.com>
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Samuel Payne authored
This patch disables SMMU hardware before suspending the SE block, for the context save operation to complete. The NS word will re-enable SMMU when we exit System Suspend. Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d Signed-off-by: Samuel Payne <spayne@nvidia.com>
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Samuel Payne authored
This patch removes the logic to set the bit that enables atomic context save/restore when we enter System suspend. The bootrom enables this bit during cold boot and exit from System Suspend, so we can remove this setting from the driver. Change-Id: Id4e08d5048155c970f5e31d9c9dd676c07182ade Signed-off-by: Samuel Payne <spayne@nvidia.com>
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- 16 Jan, 2019 7 commits
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Sam Payne authored
This patch enables L2 error correction and parity protection for Tegra210 on boot and exit from suspend. The previous bootloader sets the boot parameter, indicating ECC reporting, only for B01 SKUs. Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Varun Wadekar authored
This patch memmaps all the IRAM memory banks during boot. The BPMP firmware might place the channels in any of the IRAMs, so it is better to map all the banks to avoid surprises. Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch updates the macros to include the newly added IRAM memory apertures. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde
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Sam Payne authored
DRBG must be initialized to guarantee SRK has a random value during suspend. This patch add a sequence to generate an SRK on boot and during resume for SE1 and SE2. This SRK value is not saved to PMC scratch, and should be overwitten during atomic suspend. Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform code generates the power domain tree. The handler to retrieve the tree should also reside in the platform code. This patch moves the plat_get_power_domain_tree_desc() to the individual platforms. Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 1 commit
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Feb, 2018 1 commit
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Andreas Färber authored
Commit fdb1964c ("xlat: Introduce MAP_REGION2() macro") added a granularity field to mmap_region_t. Tegra platforms were using the v2 xlat_tables implementation in common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c where arrays are being defined. This caused the next physical address to be read as granularity, causing EINVAL error and triggering an assert. Consistently use xlat_tables_v2.h header to avoid this. Fixes ARM-software/tf-issues#548. Signed-off-by: Andreas Färber <afaerber@suse.de>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 14 Jun, 2017 1 commit
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Varun Wadekar authored
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 01 May, 2017 2 commits
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Varun Wadekar authored
This patch implements the handler to calculate the cluster and system power states for the Tegra210 SoC. The power states returned by this handler are used by the PSCI library to decide cache maintenance operations - cluster v cpu. Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Steven Kao authored
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 20 Mar, 2017 1 commit
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Andre Przywara authored
The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by erratum 855873. Enable the workaround that TF provides to fix this erratum. Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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