- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Oct, 2018 2 commits
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Andre Przywara authored
PSCI requires a core to turn itself off, which we can't do properly by just executing an algorithm on that very core. As a consequence we just put a core into WFI on CPU_OFF right now. To fix this let's task the "arisc" management processor (an OpenRISC core) with that task of asserting reset and turning off the core's power domain. We use a handcrafted sequence of OpenRISC instructions to achieve this, and hand this data over to the new sunxi_execute_arisc_code() routine. The commented source code for this routine is provided in a separate file, but the ATF code contains the already encoded instructions as data. The H6 uses the same algorithm, but differs in the MMIO addresses, so provide a SoC (family) specific copy of that code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
So far we have a sunxi_private.h header file in the common code directory. This holds the prototypes of various functions we share in *common* code. However we will need some of those in the platform specific code parts as well, and want to introduce new functions shared across the whole platform port. So move the sunxi_private.h file into the common/include directory, so that it becomes visible to all parts of the platform code. Fix up the existing #includes and add missing ones, also add the sunxi_read_soc_id() prototype here. This will be used in follow up patches. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Sep, 2018 1 commit
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Icenowy Zheng authored
The AXP805 PMIC used with H6 is capable of shutting down the system. Add support for using it to shut down the system power. The original placeholder power off code is moved to A64 code, as it's still TODO to implement PMIC operations for A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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- 28 Jun, 2018 1 commit
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Andre Przywara authored
The DRAM controller supports up to 4GB of DRAM, and there are actually boards out there where we can use at least 3GB of this. Relax the PSCI entry point check, to be not restricted to 2GB of DRAM. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 15 Jun, 2018 3 commits
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Samuel Holland authored
The reset vector entry point is preserved across CPU resets, so it only needs to be set once at boot. Hotplugged CPUs are not actually powered down, but are put in a wfi with the GIC disconnected. With this commit, Linux is able to enable, hotplug and use all four CPUs. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Samuel Holland authored
sun50i_cpu_on will be used by the PSCI implementation to initialize secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by PSCI directly, because it is not possible for a CPU to use this function to power itself down. Power cannot be shut off until the outputs are clamped, and MMIO does not work once the outputs are clamped. But at least CPU0 can shutdown the other cores early in the BL31 boot process and before shutting down the system. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Samuel Holland authored
This platform supports Allwinner's SoCs with ARMv8 cores. So far they all sport a single cluster of Cortex-A53 cores. "sunxi" is the original code name used for this platform, and since it appears in the Linux kernel and in U-Boot as well, we use it here as a short file name prefix and for identifiers. This port includes BL31 support only. U-Boot's SPL takes the role of the primary loader, also doing the DRAM initialization. It then loads the rest of the firmware, namely ATF and U-Boot (BL33), then hands execution over to ATF. This commit includes the basic platform code shared across all SoCs. There is no platform.mk yet. [Andre: moved files into proper directories, supported RESET_TO_BL31, various clean ups and simplifications ] Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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