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  1. 19 Jul, 2021 1 commit
  3. 17 Jul, 2021 1 commit
  5. 16 Jul, 2021 1 commit
  7. 12 Jul, 2021 2 commits
  9. 10 Jul, 2021 2 commits
    • Pali Rohár's avatar
      fix(plat/marvell/a3k): Fix check for external dependences · 2baf5038
      Pali Rohár authored 
      

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
      2baf5038
    • Pali Rohár's avatar
      fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set · 528dafc3
      Pali Rohár authored 
      

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.

TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.

So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
      528dafc3
  11. 30 Jun, 2021 1 commit
  13. 29 Jun, 2021 2 commits
  15. 28 Jun, 2021 1 commit
    • Max Shvetsov's avatar
      feat(sve): enable SVE for the secure world · 0c5e7d1c
      Max Shvetsov authored 
      

Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
      0c5e7d1c
  17. 23 Jun, 2021 2 commits
  19. 14 Jun, 2021 1 commit
  21. 08 Jun, 2021 1 commit
    • Jacky Bai's avatar
      docs(imx8m): update build support for imx8mq · e3c07d2f
      Jacky Bai authored 
      

Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT mean that
imx8mq will be dropped by NXP. NXP will still actively
maintain it in NXP official release.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9
      e3c07d2f
  23. 01 Jun, 2021 1 commit
  25. 25 May, 2021 3 commits
  27. 17 May, 2021 1 commit
  29. 13 May, 2021 1 commit
  31. 12 May, 2021 1 commit
  33. 10 May, 2021 1 commit
  35. 07 May, 2021 1 commit
  37. 05 May, 2021 2 commits
  39. 04 May, 2021 1 commit
  41. 30 Apr, 2021 3 commits
  43. 29 Apr, 2021 1 commit
  45. 28 Apr, 2021 2 commits
  47. 27 Apr, 2021 2 commits
    • Pali Rohár's avatar
      plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC · f2800a47
      Pali Rohár authored 
      

This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.

By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.

Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.

Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
      f2800a47
    • Aditya Angadi's avatar
      feat(plat/sgi): introduce platform variant build option · cfe1506e
      Aditya Angadi authored 
      

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.

An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1

Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      cfe1506e
  49. 26 Apr, 2021 1 commit
    • Chris Kay's avatar
      docs(license): rectify `arm-gic.h` license · 3dbbbca2
      Chris Kay authored 
      

The `arm-gic.h` file distributed by the Linux kernel is disjunctively
dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause
license has been applied in violation of the requirements of both
licenses. This change ensures the file is correctly licensed under the
terms of the MIT license, and that we comply with it by distributing a
copy of the license text.

Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
      3dbbbca2
  51. 23 Apr, 2021 3 commits
  53. 21 Apr, 2021 1 commit
    • Yann Gautier's avatar
      Add PIE support for AARCH32 · 4324a14b
      Yann Gautier authored 
      

Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.

Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      4324a14b