1. 04 Dec, 2018 2 commits
    • Igal Liberman's avatar
      mvebu: cp110: avoid pcie power on/off sequence when called from Linux · 55df84f9
      Igal Liberman authored
      
      
      In Armada 8K DB boards, PCIe initialization can be executed only once
      because PCIe reset performed during chip power on and it cannot be
      executed via GPIO later.
      This means that power on can be executed only once, when it's called
      from the bootloader.
      Power on:
      	Read bit 21 of the mode, it marks if the caller is
      	the bootloader or the Linux Kernel.
      Power off:
      	Check if the comphy was already configured to PCIe, if yes,
      	check if the caller is bootloader, if both conditions are true
      	(PCIe mode and called by Linux) - skip the power-off.
      
      In addition, fix incorrect documentation describing mode fields -
      PCIe width is 3 bits, not 2.
      
      NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
      with it).
      
      Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
      Signed-off-by: default avatarIgal Liberman <igall@marvell.com>
      Reviewed-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      Reviewed-by: default avatarKostya Porotchkin <kostap@marvell.com>
      55df84f9
    • Grzegorz Jaszczyk's avatar
      plat: marvell: a3700: do not power off cpu due to errata ref #13 · 9cb6751d
      Grzegorz Jaszczyk authored
      
      
      Do not power off the CPU1 since there is no way to wake it up
      (wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata
      Ref #13 [In power saving mode, both cores must be powered off]:
      "When Core 0 is on and Core 1 is in power-off state, a Core 1
      wake-up resets Core 0 as well and puts Core 0 back to ROM".
      
      To overcome described HW bug instead of powering the CPU off, let it
      reach WFI instruction, which is invoked by generic psci_do_cpu_off
      function after platform handler finishes. This will put the core in low
      power state and give a chance to wake it up.
      
      Before this change, after running secondary kernel via kexec, only one
      core was up, now both cores are up.
      
      Change-Id: I87f144867550728055d9b8a2edb84a14539acab7
      Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      Reviewed-by: default avatarKostya Porotchkin <kostap@marvell.com>
      9cb6751d
  2. 15 Nov, 2018 2 commits
  3. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored
      
      
      All identifiers, regardless of use, that start with two underscores are
      reserved. This means they can't be used in header guards.
      
      The style that this project is now to use the full name of the file in
      capital letters followed by 'H'. For example, for a file called
      "uart_example.h", the header guard is UART_EXAMPLE_H.
      
      The exceptions are files that are imported from other projects:
      
      - CryptoCell driver
      - dt-bindings folders
      - zlib headers
      
      Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  4. 31 Oct, 2018 1 commit
    • Konstantin Porotchkin's avatar
      plat: marvell: Add support for Armada-37xx SoC platform · 1e66bacb
      Konstantin Porotchkin authored
      
      
      Add supprot for Marvell platforms based on Armada-37xx SoC.
      This includes support for the official Armada-3720 modular
      development board and EspressoBin community board.
      The Armada-37xx SoC contains dual Cortex-A53 Application CPU,
      single secure CPU (Cortex-M3) and the following interfaces:
      - SATA 3.0
      - USB 3.0 and USB 2.0
      - PCIe
      - SDIO (supports boot from eMMC)
      - SPI
      - UART
      - I2c
      - Gigabit Ethernet
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      1e66bacb
  5. 25 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Add plat_crash_console_flush to platforms without it · 9c675b37
      Antonio Nino Diaz authored
      
      
      Even though at this point plat_crash_console_flush is optional, it will
      stop being optional in a following patch.
      
      The console driver of warp7 doesn't support flush, so the implementation
      is a placeholder.
      
      TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but
      they weren't global so they weren't actually used. Also, they were
      calling the wrong functions.
      
      imx8_helpers.S only has placeholders for all of the functions.
      
      Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      9c675b37
  6. 22 Oct, 2018 1 commit
  7. 18 Oct, 2018 1 commit
    • Grzegorz Jaszczyk's avatar
      mvebu: cp110: introduce COMPHY porting layer · 42a29337
      Grzegorz Jaszczyk authored
      
      
      Some of COMPHY parameters depends on the hw connection between the SoC
      and the PHY, which can vary on different boards e.g. due to different
      wires length. Define the "porting layer" with some defaults
      parameters. It ease updating static values which needs to be updated due
      to board differences, which are now grouped in one place.
      
      Example porting layer for a8k-db is under:
      plat/marvell/a8k/a80x0/board/phy-porting-layer.h
      
      If for some boards parameters are not defined (missing
      phy-porting-layer.h), the default values are used
      (drivers/marvell/comphy/phy-default-porting-layer.h)
      and the following compilation warning is show:
      "Using default comphy params - you may need to suit them to your board".
      
      The common COMPHY driver code is extracted in order to be shared with
      future COMPHY driver for A3700 SoC platforms
      Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      Signed-off-by: default avatarIgal Liberman <igall@marvell.com>
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      42a29337
  8. 10 Oct, 2018 1 commit
  9. 07 Oct, 2018 1 commit
  10. 03 Oct, 2018 1 commit
    • Konstantin Porotchkin's avatar
      marvell: Move BLE from external repo to the platform folder · 37c4341b
      Konstantin Porotchkin authored
      
      
      The BLE is the pre-TF-A boot stage required by Marvell Armada
      BootROM for bringing up DRAM and allow the boot image copy to it.
      Since this is not a standard boot level and only uses the TF-A
      as a build environment, it was introduced out of source tree.
      However it turns out that such remote location introduces additional
      complexity to the upstream TF-A build process.
      In order to simplify the build environment the BLE source folder
      is relocated from the external repository to A8K platform directory.
      The build documentation is updated accordingly.
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      37c4341b
  11. 02 Oct, 2018 1 commit
  12. 28 Sep, 2018 1 commit
  13. 19 Sep, 2018 1 commit
    • Andre Przywara's avatar
      drivers: i2c: mentor: move platform code into header files · dfc0fb27
      Andre Przywara authored
      
      
      At the moment we have two I2C stub drivers (for the Allwinner and the
      Marvell platform), which #include the actual .c driver file.
      Change this into the more usual design, by renaming and moving the stub
      drivers into platform specific header files and including these from the
      actual driver file. The platform specific include directories make sure
      the driver picks up the right header automatically.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      dfc0fb27
  14. 05 Sep, 2018 1 commit
  15. 03 Sep, 2018 4 commits
  16. 02 Sep, 2018 5 commits
  17. 19 Aug, 2018 1 commit
  18. 10 Aug, 2018 1 commit
  19. 18 Jul, 2018 2 commits