- 22 May, 2019 2 commits
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Paul Beesley authored
These are no longer needed as there will always be a table of contents rendered to the left of every page. Some of these lists can be quite long and, when opening a page, the reader sees nothing but a huge list of contents! After this patch, the document contents are front-and-centre and the contents are nicely rendered in the sidebar without duplication. Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
This patch attempts to standardise the document titles as well as adding titles to documents that were missing one. The aim is to remove needless references to "TF-A" or "Trusted Firmware" in the title of every document and to make sure that the title matches with the document content. Change-Id: I9b93ccf43b5d57e8dc793a5311b8ed7c4dd245cc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 21 May, 2019 1 commit
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Paul Beesley authored
This change creates the following directories under docs/ in order to provide a grouping for the content: - components - design - getting_started - perf - process In each of these directories an index.rst file is created and this serves as an index / landing page for each of the groups when the pages are compiled. Proper layout of the top-level table of contents relies on this directory/index structure. Without this patch it is possible to build the documents correctly with Sphinx but the output looks messy because there is no overall hierarchy. Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 01 Mar, 2019 2 commits
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Sandrine Bailleux authored
Some of the sections numbers have been incorrect since the document structure has changed. Using references to sections rather than hard-coded section numbers fixes the issue while making it more future-proof to updates. Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
While converting the interrupt framework design document from Markdown to reStructuredText format, see commit 6f625747 ("Convert documentation to reStructuredText"), the structure of the document was changed and one of the titles got lost. Fix that. Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 08 Feb, 2019 1 commit
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Sandrine Bailleux authored
Just like has been done in the porting guide a couple of patches earlier, kill all escaped underscore characters in all documents. Change-Id: I7fb5b806412849761d9221a6ce3cbd95ec43d611 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 26 Nov, 2018 1 commit
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Jeenu Viswambharan authored
Change-Id: I77d38758d18ba6dda1652b1b1e644fbfb14386cc Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 15 Mar, 2018 1 commit
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Dan Handley authored
Update Arm Trusted Firmware references in the upstream documents to Trusted Firmware-A (TF-A). This is for consistency with and disambiguation from Trusted Firmware-M (TF-M). Also update other Arm trademarks, e.g. ARM->Arm, ARMv8->Armv8-A. Change-Id: I8bb0e18af29c6744eeea2dc6c08f2c10b20ede22 Signed-off-by: Dan Handley <dan.handley@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
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- 06 Feb, 2018 3 commits
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Jeenu Viswambharan authored
Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how Non-secure interrupt affects TSPs execution. When TSP is executing: 1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received at the TSP's exception vector, and TSP voluntarily preempts itself. 2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a trap to EL3, which preempts TSP execution. When EL3 exception handling is in place (i.e., EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system with GICv3, pending NS interrupts while TSP is executing will be signalled as FIQ (which traps to EL3). This situation necessitates the same treatment applied to case (2) above. Therefore, when EL3 exception handling is in place, additionally require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1. Strictly speaking, this is not required on a system with GICv2, but the same model is uniformly followed regardless, for simplicity. Relevant documentation updated. Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1, EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and secure execution. The interrupt management framework currently treats EL3 interrupt routing as valid. For the above reason, this patch makes them invalid when EL3_EXCEPTION_HANDLING is in effect. Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 29 Jun, 2017 1 commit
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Douglas Raillard authored
Due to recent issues in the rendering of the documentation on GitHub and some long-standing issues like the lack of automatic table of content in Markdown, the documentation has been converted to reStructuredText. Basic constructs looks pretty similar to Markdown. Automatically convert GitHub markdown documentation to reStructuredText using pandoc. Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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