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  1. 31 Aug, 2020 1 commit
    • anzhou's avatar
      Tegra: platform specific BL31_SIZE · 5a22eb42
      anzhou authored 
      

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.
Signed-off-by: default avataranzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82
      5a22eb42
  3. 28 Aug, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra: memctrl: platform setup handler functions · 08e60f80
      Varun Wadekar authored 
      

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.

This patch creates a setup handler for a platform to implement its
initialization sequence.

Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08e60f80
    • Anthony Zhou's avatar
      Tegra: sip: add VPR resize enabled check · e9b9c2c8
      Anthony Zhou authored 
      

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      e9b9c2c8
  5. 19 Mar, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra186: system resume from TZSRAM memory · 2139c9c8
      Varun Wadekar authored 
      

TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.

This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.

Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2139c9c8
    • Varun Wadekar's avatar
      Tegra186: disable PROGRAMMABLE_RESET_ADDRESS · 8336c94d
      Varun Wadekar authored 
      

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.

Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8336c94d
  7. 11 Mar, 2020 2 commits
    • Pritesh Raithatha's avatar
      Tegra: smmu: remove context save sequence · a391d494
      Pritesh Raithatha authored 
      

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      a391d494
    • Varun Wadekar's avatar
      Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194 · e9044480
      Varun Wadekar authored 
      

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e9044480
  9. 09 Mar, 2020 2 commits
    • Jeetesh Burman's avatar
      Tegra186: add SE support to generate SHA256 of TZRAM · 4eed9c84
      Jeetesh Burman authored 
      

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      4eed9c84
    • Jeetesh Burman's avatar
      Tegra186: add support for bpmp_ipc driver · 3827aa8a
      Jeetesh Burman authored 
      

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      3827aa8a
  11. 31 Jan, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: per-SoC DRAM base values · 5f1803f9
      Varun Wadekar authored 
      

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.

Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5f1803f9
  13. 31 Jan, 2019 2 commits
    • Steven Kao's avatar
      Tegra: platform dependent address space sizes · 1d11f73e
      Steven Kao authored 
      

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      1d11f73e
    • Jeetesh Burman's avatar
      Tegra: SiP: set GPU in reset after vpr resize · 3e28e935
      Jeetesh Burman authored 
      

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      3e28e935
  15. 23 Jan, 2019 7 commits
  17. 18 Jan, 2019 4 commits
    • Harvey Hsieh's avatar
      Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO · 70da35b0
      Harvey Hsieh authored 
      

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: default avatarHarvey Hsieh <hhsieh@nvidia.com>
      70da35b0
    • Anthony Zhou's avatar
      Tegra: fix defects flagged by MISRA Rule 10.3 · aa64c5fb
      Anthony Zhou authored 
      

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      aa64c5fb
    • Anthony Zhou's avatar
      Tegra: common: drivers: fix MISRA defects · 61beb3e0
      Anthony Zhou authored 
      

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]

Voided non c-library functions whose return types are not used
 [Rule 17.7]

Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      61beb3e0
    • Varun Wadekar's avatar
      Tegra: gpcdma: driver for general purpose DMA · 647d4a03
      Varun Wadekar authored 
      

This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory copy operations to/from DRAM and TZSRAM.

This patch introduces a macro 'USE_GPC_DMA' to allow platforms
to override CPU based memory operations.

Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      647d4a03
  19. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  21. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored 
      

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  23. 15 Jun, 2017 2 commits
  25. 03 May, 2017 1 commit
  27. 01 May, 2017 2 commits
  29. 13 Apr, 2017 1 commit
  31. 07 Apr, 2017 3 commits
  33. 05 Apr, 2017 4 commits
  35. 30 Mar, 2017 2 commits