- 27 Apr, 2021 1 commit
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Pali Rohár authored
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by:Pali Rohár <pali@kernel.org> Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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- 20 Apr, 2021 12 commits
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Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by:Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by:
Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by:
Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by:
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by:
Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by:
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Konstantin Porotchkin authored
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by:
Ofer Heifetz <oferh@marvell.com> Reviewed-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by:
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Alex Leibovich authored
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by:
Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by:
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Grzegorz Jaszczyk authored
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services. Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by:
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Konstantin Porotchkin authored
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by:
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- 25 Feb, 2021 2 commits
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Konstantin Porotchkin authored
This patch cleans up the MSS SRAM if it was used for MSS image copy (secure boot mode). Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313 Signed-off-by:
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Konstantin Porotchkin authored
Map IO WIN to CP1 and CP2 at all stages including the BLE. Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly. This patch allows access to CP1/CP2 internal registers at BLE stage if CP1/CP2 are connected. Signed-off-by:
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- 24 Feb, 2021 1 commit
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Konstantin Porotchkin authored
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA. In secure boot mode the MSS DMA is unable to directly load the MSS FW image from DRAM to IRAM. This patch adds support for using the MSS SRAM as intermediate storage. The MSS FW image is loaded by application CPU into the MSS SRAM first, then transferred to MSS IRAM by MSS DMA. Such change allows the CP MSS image load in secure mode. Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712 Signed-off-by:
Grzegorz Jaszczyk <jaszczyk@marvell.com>
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- 11 Feb, 2021 2 commits
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Konstantin Porotchkin authored
The DRAM port code issues a dummy write to SPD page-0 i2c address in order to select this page for the forthcoming read transaction. If the write buffer length supplied to i2c_write is not zero, this call is translated to 2 bus transations: - set the target offset - write the data to the target However no actual data should be transferred to SPD page-0 in order to select it. Actually, the second transation never receives an ACK from the target device, which caused the following error report: ERROR: Status 30 in write transaction This patch sets the buffer length in page-0 select writes to zero, leading to bypass the data transfer to the target device. Issuing the target offset command to SPD page-0 address effectively selects this page for the read operation. Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017 Signed-off-by:
Moti Buskila <motib@marvell.com>
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Konstantin Porotchkin authored
Add initialization for TRNG-IP-76 driver and support SMC call 0xC200FF11 used for reading HW RNG value by secondary bootloader software for KASLR support. Signed-off-by:
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- 29 Jan, 2021 10 commits
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Pali Rohár authored
It does not have to be supported by the current shell used in Makefile. Replace it by a simple echo with implicit newline. Signed-off-by: -
Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
This change separates building of flash and UART images, so it is possible to build only one of these images. Also this change allows make to build them in parallel. Target mrvl_flash now builds only flash image and mrvl_uart only UART image. This change reflects it also in the documentation. Signed-off-by: -
Pali Rohár authored
This removes need to move files and also allows to build uart and flash images in parallel. Signed-off-by: -
Pali Rohár authored
Currently a3700_common.mk makefile builds intermediate files in TF-A top level directory and also outside of the TF-A tree. This change fixes this issue and builds all intermediate files in $(BUILD_PLAT) directory. Part of this change is also removal of 'rm' and 'mv' commands as there is no need to remove or move intermediate files from outside of the TF-A build tree. Signed-off-by: -
Pali Rohár authored
When building WTMI image we need to correctly set DDR_TOPOLOGY and CLOCKSPRESET variables which WTMI build system expect. Otherwise it use default values. Signed-off-by: -
Pali Rohár authored
This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and CRYPTOPP_INCDIR, which can be used to specify directory paths to pre-compiled Crypto++ library and header files. When both new parameters are specified then the source code of Crypto++ via CRYPTOPP_PATH parameter is not needed. And therefore it allows TF-A build process to use system Crypto++ library. Signed-off-by:
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- 28 Jan, 2021 1 commit
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Pali Rohár authored
plat: marvell: armada: a3k: Add checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined These variables must contain a path to a valid directory (not a file) which really exists. Also WTP and MV_DDR_PATH must point to either a valid Marvell release tarball or git repository. Signed-off-by:
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- 11 Jan, 2021 1 commit
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Marek Behún authored
The current configuration of CPU windows on Armada 37x0 with 4 GB DRAM can only utilize 3.375 GB of memory. This is because there are only 5 configuration windows, configured as such (in hexadecimal, also showing ranges not configurable by CPU windows): 0 - 80000000 | 2 GB | DDR | CPU window 0 80000000 - C0000000 | 1 GB | DDR | CPU window 1 C0000000 - D0000000 | 256 MB | DDR | CPU window 2 D0000000 - D2000000 | 32 MB | | Internal regs empty space | | | D8000000 - D8010000 | 64 KB | | CCI regs empty space | | | E0000000 - E8000000 | 128 MB | DDR | CPU window 3 E8000000 - F0000000 | 128 MB | PCIe | CPU window 4 empty space | | | FFF00000 - end | 64 KB | | Boot ROM This can be improved by taking into account that: - CCI window can be moved (the base address is only hardcoded in TF-A; U-Boot and Linux will not break with changing of this address) - PCIe window can be moved (upstream U-Boot can change device-tree ranges of PCIe if PCIe window is moved) Change the layout after the Internal regs as such: D2000000 - F2000000 | 512 MB | DDR | CPU window 3 F2000000 - FA000000 | 128 MB | PCIe | CPU window 4 empty space | | | FE000000 - FE010000 | 64 KB | | CCI regs empty space | | | FFF00000 - end | 64 KB | | Boot ROM (Note that CCI regs base address is moved from D8000000 to FE000000 in all cases, not only for the configuration with 4 GB of DRAM. This is because TF-A is built with this address as a constant, so we cannot change this address at runtime only on some boards.) This yields 3.75 GB of usable RAM. Moreover U-Boot can theoretically reconfigure the PCIe window to DDR if it discovers that no PCIe card is connected. This can add another 128 MB of DRAM (resulting only in 128 MB of DRAM not being used). Signed-off-by:Marek Behún <marek.behun@nic.cz> Change-Id: I4ca1999f852f90055fac8b2c4f7e80275a13ad7e
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- 07 Jan, 2021 1 commit
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Pali Rohár authored
Only non-file targets should be set a .PHONY. Otherwise if file target is set as .PHONY then targets which depends on those file .PHONY targets would be always rebuilt even when their prerequisites are not changed. File target which needs to be always rebuilt can be specified in Make system via having a prerequisite on some .PHONY target, instead of marking whole target as .PHONY. In Makefile projects it is common to create empty .PHONY target named FORCE for this purpose. This patch changes all file targets which are set as .PHONY to depends on new .PHONY target FORCE, to ensure that these file targets are always rebuilt (as before). Basically they are those targets which calls external make subprocess. After FORCE target is specified in main Makefile, remove it from other Makefile files to prevent duplicate definitions. Signed-off-by:
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- 05 Jan, 2021 1 commit
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Marek Behún authored
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which, when enabled, adds code to the PSCI reset handler to try to do system reset by the WTMI firmware running on the Cortex-M3 secure coprocessor. (This function is exposed via the mailbox interface.) The reason is that the Turris MOX board has a HW bug which causes reset to hang unpredictably. This issue can be solved by putting the board in a specific state before reset. Signed-off-by:
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- 07 Dec, 2020 8 commits
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Pali Rohár authored
Signed-off-by: -
Pali Rohár authored
These two targets are build by make subprocesses and are independent. So splitting them into own targets allow make to build them in parallel. $(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile. Signed-off-by: -
Pali Rohár authored
Add check when building mrvl_bootimage that size of bl1 image is not bigger than maximal size. Signed-off-by: -
Pali Rohár authored
FORCE target is used as a dependency for other file targets which needs to be always rebuilt. .PHONY target is standard Makefile target which specify non-file targets and therefore needs to be always rebuilt. Targets clean, realclean and distclean are .PHONY targets used to remove built files. Correctly set that mrvl_clean target is prerequisite for these clean targets to ensure that built files are removed. Finally this change with usage of FORCE target allows to remove mrvl_clean hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess. Signed-off-by: -
Pali Rohár authored
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Pali Rohár authored
Signed-off-by: -
Pali Rohár authored
Create copy of WTMI images instead of moving them into TF-A build directory. Signed-off-by: -
Pali Rohár authored
Rather create a temporary copy in $(BUILD_PLAT) and modify only copy. Signed-off-by:
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