- 15 Jan, 2020 4 commits
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Rajan Vaja authored
Add new QID to get maximum supported divisor by clock. Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by:
Tejas Patel <tejas.patel@xilinx.com> Signed-off-by:
Jolly Shah <jolly.shah@xilinx.com> Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a
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Ravi Patel authored
Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by:
Ravi Patel <ravi.patel@xilinx.com> Signed-off-by:
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Rajan Vaja authored
Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by:
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Rajan Vaja authored
Add support to add extra custom type flags and provide to caller in topology query. Signed-off-by:
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- 07 Jan, 2020 4 commits
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Rajan Vaja authored
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by:
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Mounika Grace Akula authored
This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by:
Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by:
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Mirela Simonovic authored
GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by:
Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by:
Will Wong <will.wong@xilinx.com> Signed-off-by:
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Mounika Grace Akula authored
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by:
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- 04 Jan, 2019 17 commits
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Jolly Shah authored
This clock does not drive any clock in LPD so there is no need for Linux to try to initialize it. Signed-off-by:
Will Wong <WILLW@xilinx.com> Signed-off-by:
Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Linux has no reason to use these system and debug clocks and therefore shouldn't access them. These clocks are marked as invalid in order to prevent Linux from registering and querying them. Note that despite clocks being marked as invalid a security issue still remains in place as there is nothing that prevents the non-secure world from gating these clocks and that way causing damage to the system. Signed-off-by:
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Jolly Shah authored
These clocks are marked as invalid in order to prevent Linux from registering them. Note that despite clocks being marked as invalid a security issue still remains in place as there is nothing that prevents the non-secure world from gating these clocks and that way halt the whole APU subsystem. Signed-off-by:
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Jolly Shah authored
In the existing model for ACPU clock the mux, divider, and gate were represented as one clock and ACPU_HALF was modelled as child of ACPU clock. This is not correct. ACPU clock model contains only mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF clocks which have only gates. The models of ACPU and ACPU_HALF clocks are fixed and ACPU_FULL clock is added. Signed-off-by:
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Jolly Shah authored
Clock get parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to get pre_src, post_src, div2 and bypasss, in the implementation of pm_clock_get_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *_PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL-specific EEMI API with the respective parameter ID. For case 2) the call is passed to the PMU. Signed-off-by:
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Jolly Shah authored
Clock set parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to set pre_src, post_src, div2 and bypass, in the implementation of pm_clock_set_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL set parameter EEMI API with the respective parameter ID. Since clock set parent interface to EL1/2 receives parent index (mux select value), the value is just passed to PMU. Functions that appear to be unused after this change is made are removed. Setting the parent of *PLL clocks, that actually model bypass, is not possible. This is already ensured by the existing clock model having the CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the bypass parent. Bypass is controlled only by the PMU firmware. Signed-off-by:
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Jolly Shah authored
Clock set/get rate are not implemented and will likely never be. Remove empty function stubs. Signed-off-by:
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Jolly Shah authored
Clock get divider EEMI API is reimplemented to use system-level clock get divider EEMI API rather than direct MMIO read/write accesses to clock control registers. Signed-off-by:
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Jolly Shah authored
Clock set divider EEMI API is reimplemented to use system-level clock set divider EEMI API rather than direct MMIO read/write accesses to clock control registers. Signed-off-by:
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Jolly Shah authored
Clock get state EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux is_enabled method for PLLs still uses clock get state API get the PLL state, in the implementation of pm_clock_getstate() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock whose state of the gate should be returned. For case 1) we'll call pm_api_clock_pll_getstate() implemented in pm_api_clock.h/c. This function will query the PLL state from PMU using the system-level PLL get mode EEMI API. For case 2) we'll call the PMU to query the clock gate state using system-level clock get status EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by:
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Jolly Shah authored
Clock disable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock disable API to reset the PLL in the implementation of pm_clock_disable() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_disable() implemented in pm_api_clock.h/c. This function will reset the PLL using the system-level PLL set mode EEMI API with the reset mode argument. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock disable EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by:
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Jolly Shah authored
Clock enable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock enable API to trigger locking of the PLLs in the pm_clock_enable() implementation we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_enable() implemented in pm_api_clock.h/c. This function checks what is the buffered PLL mode and calls the system-level PLL set mode EEMI API with the buffered mode value specified as argument. Long term, if linux driver get fixed to use PLL EEMI API to control PLLs, this case could be removed from ATF. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock enable EEMI API. Signed-off-by:
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Jolly Shah authored
When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual mode to be read from hardware, but the value that it is intending to program. Therefore, we return the buffered value to linux. Signed-off-by:
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Jolly Shah authored
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the fractional mode to be changed in hardware. Furthermore, even before this patch setting the mode which is done by writing into register takes no effect until the PLL reset is deasserted, i.e. until linux "enables" the PLL. To adjust the code to system-level PLL EEMI API and avoid unnecessary IPIs that would otherwise be issued, we buffer the mode value set via IOCTL until the PLL mode really needs to be set. Signed-off-by:
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Jolly Shah authored
Fractional data should be set using PLL set parameter EEMI API. This stands for system-level communication (APU to PMU). Since linux already uses a specific IOCTL function to do this and we need to keep it that way, the pll clock ID given by linux has to be mapped to the pll node ID that is communicated at the system-level (argument of PLL set parameter API). With this modification the function pm_api_clk_set_pll_frac_data is removed from pm_api_clock.c/h because it became unused. Signed-off-by:
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Jolly Shah authored
Fractional data should be get using PLL get parameter EEMI API. This stands for system-level communication (APU to PMU). Since linux already uses a specific IOCTL function to do this and we need to keep it that way, the pll clock ID given by linux has to be mapped to the pll node ID that is communicated at the system-level (argument of PLL get parameter API). With this modification the function pm_api_clk_get_pll_frac_data is removed from pm_api_clock.c/h because it became unused. The clock enum is defined as 'enum clock_id'. Signed-off-by:
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by:Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Sep, 2018 4 commits
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Rajan Vaja authored
Correct function header of pm_api_clock_getparent() and pm_api_clock_setparent(). Signed-off-by:
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Siva Durga Prasad Paladugu authored
PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable them based on their user count. So, it should not be handled from ATF. Put PLL type clock into bypass and reset mode only while changing PLL rate (FBDIV). Signed-off-by:
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
CCF has already provision to enable clock during registration through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of init_enable attribute. Signed-off-by:
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Siva Durga Prasad Paladugu authored
WDT used by APU is FPD_WDT. FPD WDT clock is controlled by FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock database. As per FPD_SLCR.WDT_CLK_SEL register, there can be only two parents of WDT clock not three. Fix the same by correcting it's parents in clock database. Signed-off-by:
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- 27 Aug, 2018 1 commit
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Rajan Vaja authored
Currently in Linux maximum number of clocks is hard-coded and so it needs to allocate static memory. It can get actual clock number after querying all clock names by special clock name string. Add new query data parameter to get actual number of clocks so Linux can get actual clock numbers in advance. Signed-off-by:
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- 15 Mar, 2018 3 commits
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Jolly Shah authored
Various changes to comply with MISRA static analysis rules Signed-off-by: -
Rajan Vaja authored
- Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by:
Rajan Vaja <rajanv@xilinx.com> Signed-off-by:
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Rajan Vaja authored
These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by:
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