- 28 Sep, 2020 1 commit
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Chandni Cherukuri authored
This patch adds support for Morello platform. It is an initial port which includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary bootloader. Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Anurag Koul <anurag.koul@arm.com>
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- 25 Sep, 2020 1 commit
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Javier Almansa Sobrino authored
This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
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- 24 Sep, 2020 2 commits
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Sami Mujawar authored
The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which indicates that the platform has mitigation for cold reboot attacks. However, the flash memory used for the mem_protect region was not mapped. This results in a crash when an OS calls PSCI MEM_PROTECT. To fix this map the flash region used for mem_protect. Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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Usama Arif authored
Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 15 Sep, 2020 3 commits
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Olivier Deprez authored
According to [1] and in context of FF-A v1.0 a secure partition must have either one EC (migratable UP) or a number of ECs equal to the number of PEs (pinned MP). Adjust the SPMC manifest such that the number of ECs is equal to the number of PEs. [1] https://trustedfirmware-a.readthedocs.io/en/latest/components/ secure-partition-manager.html#platform-topology Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ie8c7d96ae7107cb27f5b97882d8f476c18e026d4
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Manish V Badarkhe authored
Increased BL2 maximum size when CoT descriptors are placed in device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I6466d2841e189e7f15eb4f1a8db070542893cb5b
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Manish V Badarkhe authored
Implemented a parser which populates the properties of the CoT descriptors as per the binding document [1]. 'COT_DESC_IN_DTB' build option is disabled by default and can be enabled in future for all Arm platforms by making necessary changes in the memory map. Currently, this parser is tested only for FVP platform. [1]: https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 14 Sep, 2020 1 commit
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Leonardo Sandoval authored
Loop macros make it easier for developers to include new variables to assert or define and also help code code readability on makefiles. Change-Id: I0d21d6e67b3eca8976c4d856ac8ccc02c8bb5ffa Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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- 10 Sep, 2020 4 commits
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Usama Arif authored
The size of debug binaries of SCP has increased beyond the current limit of 80kB set in platform. Hence, increase it to 128kB. Change-Id: I5dbcf87f8fb35672b39abdb942c0691fb339444a Signed-off-by: Usama Arif <usama.arif@arm.com>
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Sandeep Tripathy authored
Use common ehf file for generic frameworks like SDEI, RAS and extend plat specific defines using 'PLAT_EHF_DESC'. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I8a8161c6030f8d226a8bdf0301e7fe6139f019a4
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Anders Dellien authored
This fixes build errors for rdn1edge Change-Id: I63f7ebff68679e1e859f8786d4def4960c0f2ddf Signed-off-by: Anders Dellien <anders.dellien@arm.com>
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Ruari Phipps authored
UUID's in the device tree files were stored in little endian. So to keep all entries in these files RFC 4122 compliant, store them in big endian then convert it to little endian when they are read so they can be used in the UUID data structure. Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: I5674159b82b245104381df10a4e3291160d9b3b5
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- 09 Sep, 2020 1 commit
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Saurabh Gorecha authored
Follwing APIs wrappers are exposed to qtiseclib * strcmp * memset * memmove Change-Id: I79d50f358239cfda607d5f1a53314aa3b8f430cb Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 07 Sep, 2020 1 commit
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Manish V Badarkhe authored
Coverity build periodically throws below errors(non-consistently) for 'QEMU' and 'RPI3' platforms. /bin/sh: 1: cannot create build/qemu/debug/rot_key.pem: Directory nonexistent plat/qemu/qemu/platform.mk:86: recipe for target 'build/qemu/debug/ rot_key.pem' failed make: *** [build/qemu/debug/rot_key.pem] Error 2 /bin/sh: 1: cannot create /work/workspace/workspace/tf-coverity/build /rpi3/debug/rot_key.pem: Directory nonexistent plat/rpi/rpi3/platform.mk:214: recipe for target '/work/workspace/ workspace/tf-coverity/build/rpi3/debug/rot_key.pem' failed make: *** [/work/workspace/workspace/tf-coverity/build/rpi3/debug/ rot_key.pem] Error 2 Issue seems to be occurred when 'ROT key' is generated before creating the platform build folder(for e.g.build/qemu/debug). Changes are made to fix this issue by adding orderly dependancy of the platform folder for the 'ROT key' creation which ensures that platform folder is created before generating 'ROT key'. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I20c82172dde84e4c7f2373c0bd095d353f845d38
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- 02 Sep, 2020 3 commits
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Alexei Fedorov authored
Trace analysis of FVP_Base_AEMv8A 0.0/6063 model running in Aarch32 mode with the build options listed below: TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem shows that when auth_signature() gets called 71.99% of CPU execution time is spent in memset() function written in C using single byte write operations, see lib\libc\memset.c. This patch introduces new libc_asm.mk makefile which replaces C memset() implementation with assembler version giving the following results: - for Aarch32 in auth_signature() call memset() CPU time reduced to 20.56%. The number of CPU instructions (Inst) executed during TF-A boot stage before start of BL33 in RELEASE builds for different versions is presented in the tables below, where: - C TF-A: existing TF-A C code; - C musl: "lightweight code" C "implementation of the standard library for Linux-based systems" https://git.musl-libc.org/cgit/musl/tree/src/string/memset.c - Asm Opt: assemler version from "Arm Optimized Routines" project https://github.com/ARM-software/optimized-routines/blob/ master/string/arm/memset.S - Asm Linux: assembler version from Linux kernel https://github.com/torvalds/linux/blob/master/arch/arm/lib/memset.S - Asm TF-A: assembler version from this patch Aarch32: +-----------+------+------+--------------+----------+ | Variant | Set | Size | Inst | Ratio | +-----------+------+------+--------------+----------+ | C TF-A | T32 | 16 | 2122110003 | 1.000000 | | C musl | T32 | 156 | 1643917668 | 0.774662 | | Asm Opt | T32 | 84 | 1604810003 | 0.756233 | | Asm Linux | A32 | 168 | 1566255018 | 0.738065 | | Asm TF-A | A32 | 160 | 1525865101 | 0.719032 | +-----------+------+------+--------------+----------+ AArch64: +-----------+------+------------+----------+ | Variant | Size | Inst | Ratio | +-----------+------+------------+----------+ | C TF-A | 28 | 2732497518 | 1.000000 | | C musl | 212 | 1802999999 | 0.659836 | | Asm TF-A | 140 | 1680260003 | 0.614917 | +-----------+------+------------+----------+ This patch modifies 'plat\arm\common\arm_common.mk' by overriding libc.mk makefile with libc_asm.mk and does not effect other platforms. Change-Id: Ie89dd0b74ba1079420733a0d76b7366ad0157c2e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Javier Almansa Sobrino authored
At the moment BL31 dynamically discovers the CPU topology of an FPGA system at runtime, but does not export it to the non-secure world. Any BL33 user would typically looks at the devicetree to learn about existing CPUs. This patch exports a minimum /cpus node in a devicetree to satisfy the binding. This means that no cpumaps or caches are described. This could be added later if needed. An existing /cpus node in the DT will make the code bail out with a message. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e
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Anders Dellien authored
This patch adds dependencies to the generated configuration files that are included in the FIP. This fixes occasional build errors that occur when the FIP happens to be built first. Change-Id: I5a2bf724ba3aee13954403b141f2f19b4fd51d1b Signed-off-by: Anders Dellien <anders.dellien@arm.com>
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- 01 Sep, 2020 1 commit
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Hsin-Yi Wang authored
Add jedec info for mt8173, mt8183, and mt8192. [1] http://www.softnology.biz/pdf/JEP106AV.pdf Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Change-Id: Iab36fd580131f0b09b27223fba0e9d1e187d9196
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- 31 Aug, 2020 7 commits
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anzhou authored
If the CPU doesn't run from BL31_BASE, the firmware needs to be copied from load address to BL31_BASE during cold boot. The size should be the actual size of the code, which is indicated by the __RELA_END__ linker variable. This patch updates the copy routine to use this variable as a result. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9
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anzhou authored
The the GIC CPU interface should be disabled after cpu off. The Tegra power management code should mark the connected core as asleep as part of the CPU off sequence. This patch disables the GICC after CPU off as a result. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea
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anzhou authored
This patch moves the BL31_SIZE to the Tegra SoC specific tegra_def.h. This helps newer platforms configure the size of the memory available for BL31. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82
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Varun Wadekar authored
This patch sanity checks the power state type before use, from the platform's PSCI handler. Verified with TFTF Standard Test Suite. Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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anzhou authored
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value. This patch fixes the anomaly and updates the driver to remove this logic. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4
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Kalyani Chidambaram Vaidyanathan authored
Tegra SoCs would like the flexibility to perform chip specific actions before we complete cold boot. This patch introduces a platform specific 'runtime_setup' handler to provide that flexibility. Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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Kalyani Chidambaram Vaidyanathan authored
The SVE CPU extension library reads the id_aa64pfr0_el1 register to check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for pre-8.2 platforms, but this flag can safely be enabled now that the library can enable the feature at runtime. This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0" as a result. Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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- 28 Aug, 2020 15 commits
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Manish V Badarkhe authored
In the case of Juno AArch32, platform security configuration gets done from both BL2 and SP_MIN(BL32) components when JUNO_AARCH32_EL3_RUNTIME and RESET_TO_SP_MIN build options are set. Fix is provided to avoid Platform security configuration from SP_MIN when it is already done in BL2. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I702e91dacb4cdd2d10e339ddeaea91289bef3229
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Manish V Badarkhe authored
Using the Fconf, register base address of the various nv-counters (currently, trusted, non-trusted nv-counters) are moved to the device tree and retrieved during run-time. This feature is enabled using the build option COT_DESC_IN_DTB. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I236f532e63cea63b179f60892cb406fc05cd5830
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Varun Wadekar authored
This patch removes the unused header from the Tegra194 platform files. As a result, the TSA MMIO would be removed from the memory map too. Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The driver initially contained the setup steps to help Tegra186 and Tegra194 SoCs. In order to support future SoCs and make sure that the driver remains generic enough, some code should be moved to SoC. This patch creates a setup handler for a platform to implement its initialization sequence. Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
The stream ID security configuration settings shall be done by the previous level bootloader. This change removes the same settings from the Tegra194 platform code as a result. Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Pritesh Raithatha authored
The stream ID override configuration is saved during System Suspend as part MB1 bct. This change removes the same support from the Tegra194 platform code as a result. Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Varun Wadekar authored
This patch adds prints to display the completion of System Suspend programming sequence for Tegra platforms. The console needs to be kept alive until the very end of the System Suspend sequence as a result. Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
After enabling the strict checking mode, verify that the strict mode has really been enabled by querying the MCE. If the mode is found to be disabled, the code should assert. Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
The Memory controller expects the TZDRAM base value at 1MB granularity and the current driver does not respect that limitation. This patch fixes that anomaly. Change-Id: I6b72270f331ba5081e19811df4a78623e457341a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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David Pu authored
In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/output parameter to specify in progress RAS error record index. The measured SMC call latency is about 20us under Linux test kernel driver. Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
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Varun Wadekar authored
The TEGRA_GICv2_SOURCES contains the list of GIC sources required to compile the GICv2 support for platforms. This patch includes the TEGRA_GICv2_SOURCES macro from individual makefiles to allow future platforms to use suport for GICv3. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb
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Varun Wadekar authored
This patch adds memory barriers to the trampoline code copying TZDRAM contents to SysRAM during exit from System Suspend. These barriers make sure that all the copies go through before we start executing in SysRAM. Reported by: Nathan Tuck <ntuck@nvidia.com> Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
The Memory Controller provides a control register to check if the video memory can be resized. The previous bootloader might have locked this feature, which will be reflected by this register. This patch reads the control register before processing a video memory resize request. An error code, -ENOTSUP, is returned if the feature is locked. Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
MMIO writes should verify that the writes actually went through. Read the value back after the write operation, perform assert if the read back value is not same as the write value. Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes the unused cortex_a53.h header file from common Tegra files. This change fixes the violation of CERTC Rule: DCL23. Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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