1. 23 May, 2014 1 commit
    • Sandrine Bailleux's avatar
      doc: Update information about the memory layout · 638363eb
      Sandrine Bailleux authored
      Rework the "Memory layout on FVP platforms" section in the Firmware
      Design document. Add information about where the TSP image fits
      in the memory layout when present.
      
      Add documentation for the base addresses of each bootloader image
      in the porting guide.
      
      Change-Id: I4afb2605e008a1cb28c44a697804f2cb6bb4c9aa
      638363eb
  2. 24 Apr, 2014 1 commit
  3. 08 Apr, 2014 2 commits
    • Sandrine Bailleux's avatar
      Define frequency of system counter in platform code · 9e86490f
      Sandrine Bailleux authored
      BL3-1 architecture setup code programs the system counter frequency
      into the CNTFRQ_EL0 register. This frequency is defined by the
      platform, though. This patch introduces a new platform hook that
      the architecture setup code can call to retrieve this information.
      In the ARM FVP port, this returns the first entry of the frequency
      modes table from the memory mapped generic timer.
      
      All system counter setup code has been removed from BL1 as some
      platforms may not have initialized the system counters at this stage.
      The platform specific settings done exclusively in BL1 have been moved
      to BL3-1. In the ARM FVP port, this consists in enabling and
      initializing the System level generic timer. Also, the frequency change
      request in the counter control register has been set to 0 to make it
      explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
      fixed in this context to give an entry number rather than a bitmask.
      
      In future, when support for firmware update is implemented, there
      is a case where BL1 platform specific code will need to program
      the counter frequency. This should be implemented at that time.
      
      This patch also updates the relevant documentation.
      
      It properly fixes ARM-software/tf-issues#24
      
      Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
      9e86490f
    • Sandrine Bailleux's avatar
      Revert "Move architecture timer setup to platform-specific code" · 65a9c0e9
      Sandrine Bailleux authored
      This reverts commit 1c297bf0
      because it introduced a bug: the CNTFRQ_EL0 register was no
      longer programmed by all CPUs.  bl31_platform_setup() function
      is invoked only in the cold boot path and consequently only
      on the primary cpu.
      
      A subsequent commit will correctly implement the necessary changes
      to the counter frequency setup code.
      
      Fixes ARM-software/tf-issues#125
      
      Conflicts:
      
      	docs/firmware-design.md
      	plat/fvp/bl31_plat_setup.c
      
      Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
      65a9c0e9
  4. 26 Mar, 2014 1 commit
    • Vikram Kanigiri's avatar
      Initialise UART console in all bootloader stages · 0796fe01
      Vikram Kanigiri authored
      This patch reworks the console driver to ensure that each bootloader stage
      initializes it independently. As a result, both BL3-1 and BL2 platform code
      now calls console_init() instead of relying on BL1 to perform console setup
      
      Fixes ARM-software/tf-issues#120
      
      Change-Id: Ic4d66e0375e40a2fc7434afcabc8bbb4715c14ab
      0796fe01
  5. 10 Mar, 2014 1 commit
    • Jeenu Viswambharan's avatar
      Move architecture timer setup to platform-specific code · 1c297bf0
      Jeenu Viswambharan authored
      At present, bl1_arch_setup() and bl31_arch_setup() program the counter
      frequency using a value from the memory mapped generic timer. The
      generic timer however is not necessarily present on all ARM systems
      (although it is architected to be present on all server systems).
      
      This patch moves the timer setup to platform-specific code and updates
      the relevant documentation. Also, CNTR.FCREQ is set as the specification
      requires the bit corresponding to the counter's frequency to be set when
      enabling. Since we intend to use the base frequency, set bit 8.
      
      Fixes ARM-software/tf-issues#24
      
      Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652
      1c297bf0
  6. 28 Feb, 2014 4 commits
    • Dan Handley's avatar
      Consolidate design and porting documentation · 57de6d72
      Dan Handley authored
      Consolidate firmware-design.md and porting-guide.pm so
      that recently added sections fit better with
      pre-existing sections. Make the documentation more
      consistent in use of terminology.
      
      Change-Id: Id87050b096122fbd845189dc2fe1cd17c3003468
      57de6d72
    • Dan Handley's avatar
      Add EL3 runtime services and SPD documentation · 5e1e9200
      Dan Handley authored
      1. Add design information on EL3 runtime services and
      Secure-EL1 Payload Dispatchers (SPD) to
      firmware-design.md.
      
      2. Create new EL3 runtime service writer's guide
      (rt-svc-writers-guide.md) to ease creation of new
      runtime services.
      
      Change-Id: I670aeb5fc246e25c6e599a15139aac886a0074fd
      5e1e9200
    • Dan Handley's avatar
      Separate firmware design out of user-guide.md · 247f60bc
      Dan Handley authored
      Move the firmware design documentation out of user-guide.md
      and into a new file - firmware-design.md. Reformat the
      section headers.
      
      Change-Id: I664815dd47011c7c1cf2202aa4472a8fd78ebb92
      247f60bc
    • Dan Handley's avatar
      Update versions of dependencies in user-guide.md · 3505c044
      Dan Handley authored
      1. Update user-guide.md with the latest versions of dependent
      components required by the tested configurations of ARM Trusted
      Firmware. This includes the tested versions of Fixed Virtual
      Platforms (FVPs), toolchain, EFI Development Kit 2(EDK2),
      Linux kernel and Linux file system.
      
      2. Remove the instructions to configure the Cortex Base FVP
      with the legacy GICv2 memory map as this is no longer supported
      since version 5.3 of the Base FVPs.
      
      3. General tidyup of "Using the software" section.
      
      Change-Id: If8264cd29036b59dc5ff435b5f8b1d072dd36ef0
      3505c044
  7. 20 Feb, 2014 3 commits
    • Achin Gupta's avatar
      Add support for BL3-2 in BL3-1 · 35ca3511
      Achin Gupta authored
      This patch adds the following support to the BL3-1 stage:
      
      1. BL3-1 allows runtime services to specify and determine the security
         state of the next image after BL3-1. This has been done by adding
         the `bl31_set_next_image_type()` & `bl31_get_next_image_type()`
         apis. The default security state is non-secure. The platform api
         `bl31_get_next_image_info()` has been modified to let the platform
         decide which is the next image in the desired security state.
      
      2. BL3-1 exports the `bl31_prepare_next_image_entry()` function to
         program entry into the target security state. It uses the apis
         introduced in 1. to do so.
      
      3. BL3-1 reads the information populated by BL2 about the BL3-2 image
         into its internal data structures.
      
      4. BL3-1 introduces a weakly defined reference `bl32_init()` to allow
         initialisation of a BL3-2 image. A runtime service like the Secure
         payload dispatcher will define this function if present.
      
      Change-Id: Icc46dcdb9e475ce6575dd3f9a5dc7a48a83d21d1
      35ca3511
    • Achin Gupta's avatar
      Add support for BL3-2 in BL2 · a3050ed5
      Achin Gupta authored
      
      
      This patch adds support for loading a BL3-2 image in BL2. In case a
      BL3-2 image is found, it also passes information to BL3-1 about where it
      is located and the extents of memory available to it. Information about
      memory extents is populated by platform specific code.
      
      The documentation has also been updated to reflect the above changes.
      
      Change-Id: I526b2efb80babebab1318f2b02e319a86d6758b0
      Co-authored-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      a3050ed5
    • Achin Gupta's avatar
      Rework BL2 to BL3-1 hand over interface · e4d084ea
      Achin Gupta authored
      This patch reworks BL2 to BL3-1 hand over interface by introducing a
      composite structure (bl31_args) that holds the superset of information
      that needs to be passed from BL2 to BL3-1.
      
        - The extents of secure memory available to BL3-1
        - The extents of memory available to BL3-2 (not yet implemented) and
          BL3-3
        - Information to execute BL3-2 (not yet implemented) and BL3-3 images
      
      This patch also introduces a new platform API (bl2_get_bl31_args_ptr)
      that needs to be implemented by the platform code to export reference to
      bl31_args structure which has been allocated in platform-defined memory.
      
      The platform will initialize the extents of memory available to BL3-3
      during early platform setup in bl31_args structure. This obviates the
      need for bl2_get_ns_mem_layout platform API.
      
      BL2 calls the bl2_get_bl31_args_ptr function to get a reference to
      bl31_args structure. It uses the 'bl33_meminfo' field of this structure
      to load the BL3-3 image. It sets the entry point information for the
      BL3-3 image in the 'bl33_image_info' field of this structure. The
      reference to this structure is passed to the BL3-1 image.
      
      Also fixes issue ARM-software/tf-issues#25
      
      Change-Id: Ic36426196dd5ebf89e60ff42643bed01b3500517
      e4d084ea
  8. 17 Feb, 2014 1 commit
  9. 30 Jan, 2014 1 commit
    • Ian Spray's avatar
      Allow style checking of tree and local changes · 36eaaf37
      Ian Spray authored
      New phony Makefile targets have been added:
      
       * checkcodebase
       * checkpatch
      
      The checkcodebase target will run a Linux style compliance check over the
      entire codebase, and honours the V=1 Makefile verbose setting and so will
      show more information when this is enabled.
      
      If the local directory is a git checkout then the output of git ls-files is
      used to decide which files to test for compliance.  If the local directory
      is not under git control then a 'best attempt' is made, but in this case it
      should be noted that it is possible for additional non-codebase files to be
      tested, so care should be taken when parsing the output.
      
      The checkpatch target will compare local changes against the git origin/master
      to allow issues with the last set of changes to be identified.  To override
      the change comparision location, set the BASE_COMMIT variable to your
      desired git branch.
      
      Both targets rely on the Linux source tree script checkpatch.pl to do the
      syntax checking, and expects that the CHECKPATCH environment variable points
      to the location of this file.
      
      Notes on the usage of these targets have been added to the contributing.md
      and docs/user-guide.md text files.
      
      Change-Id: I6d73c97af578e24a34226d972afadab9d30f1d8d
      36eaaf37
  10. 20 Jan, 2014 1 commit
  11. 17 Jan, 2014 2 commits
    • Harry Liebel's avatar
      Do not trap access to floating point registers · 4f603683
      Harry Liebel authored
      Traps when accessing architectural features are disabled by clearing bits
      in CPTR_EL3 during early boot, including accesses to floating point
      registers. The value of this register was previously undetermined, causing
      unwanted traps to EL3. Future EL3 code (for example, context save/restore
      code) may use floating point registers, although they are not used by current
      code.
      
      Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to
      prevent generation of code that uses floating point registers.
      
      Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747
      4f603683
    • Dan Handley's avatar
      Update year in copyright text to 2014 · e83b0cad
      Dan Handley authored
      Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
      e83b0cad
  12. 05 Dec, 2013 3 commits
    • Achin Gupta's avatar
      psci: update docs with status of cpu_suspend api · dc98e537
      Achin Gupta authored
      This patch makes changes to the documents to reflect the current
      state of play of the psci cpu_suspend function.
      
      Change-Id: I086509fb75111b6e9f93b7f6dbcd33cc4591b9f3
      dc98e537
    • Dan Handley's avatar
      Enable third party contributions · ab2d31ed
      Dan Handley authored
      - Add instructions for contributing to ARM Trusted Firmware.
      
      - Update copyright text in all files to acknowledge contributors.
      
      Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
      ab2d31ed
    • Sandrine Bailleux's avatar
      Update user guide further to linker scripts changes · cd29b0a6
      Sandrine Bailleux authored
      This patch updates the user guide section about the memory layout.
        - Explain the verifications that the linker scripts does on the
          global memory layout.
        - Refer to the new linker symbols.
        - Describe the linker symbols exported to the trusted firmware code.
      
      Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286
      cd29b0a6
  13. 27 Nov, 2013 3 commits
    • James Morrissey's avatar
      Generate build products in sub-directories · eaaeece2
      James Morrissey authored
      A single binary can be compiled using a command such as:
        make CROSS_COMPILE=aarch64-none-elf- bl1
      
      Also make use of brackets consistent in the Makefile.
      
      Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e
      eaaeece2
    • Harry Liebel's avatar
      Increase default amount of RAM for Base FVPs in FDTs · 375ae68e
      Harry Liebel authored
      - Large RAM-disks may have trouble starting with 2GB of memory.
      - Increase from 2GB to 4GB in FDT.
      
      Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7
      375ae68e
    • Sandrine Bailleux's avatar
      Unmask SError and Debug exceptions. · 3738274d
      Sandrine Bailleux authored
      Any asynchronous exception caused by the firmware should be handled
      in the firmware itself.  For this reason, unmask SError exceptions
      (and Debug ones as well) on all boot paths.  Also route external
      abort and SError interrupts to EL3, otherwise they will target EL1.
      
      Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
      3738274d
  14. 14 Nov, 2013 2 commits
  15. 25 Oct, 2013 1 commit