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  1. 29 Jun, 2021 1 commit
    • Sandrine Bailleux's avatar
      refactor(plat/fvp): tidy up list of images to measure · 64dd1dee
      Sandrine Bailleux authored 
      

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      64dd1dee
  3. 17 Jun, 2021 2 commits
  5. 15 Jun, 2021 5 commits
  7. 12 Jun, 2021 2 commits
  9. 04 Jun, 2021 3 commits
  11. 03 Jun, 2021 5 commits
  13. 02 Jun, 2021 2 commits
    • Yann Gautier's avatar
      fix(plat/arm): correct UUID strings in FVP DT · 748bdd19
      Yann Gautier authored 
      

The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined
in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and
TRUSTED_KEY_CERT.
Signed-off-by: default avatarYann Gautier <yann.gautier@foss.st.com>
Change-Id: I517f8f9311585931f2cb931e0588414da449b694
      748bdd19
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART parent clock rate determination · 5a91c439
      Pali Rohár authored 
      

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
      5a91c439
  15. 01 Jun, 2021 3 commits
  17. 31 May, 2021 2 commits
  19. 28 May, 2021 2 commits
    • johpow01's avatar
      fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs · c6ac4df6
      johpow01 authored 
      

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
      c6ac4df6
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation · 66a77528
      Pali Rohár authored 
      

UART parent clock is by default the platform's xtal clock, which is
25 MHz.

The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
  Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.

Change the code for divisor calculation to
  Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to 25 MHz.

The final UART divisor for default baudrate 115200 is not affected by
this change.

(Note that the parent clock rate should not be defined via a macro,
since the xtal clock can also be 40 MHz. This is outside of the scope of
this fix, though.)
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
      66a77528
  21. 27 May, 2021 7 commits
  23. 26 May, 2021 3 commits
  25. 25 May, 2021 3 commits