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  1. 09 Mar, 2020 1 commit
    • Jeetesh Burman's avatar
      Tegra186: add SE support to generate SHA256 of TZRAM · 4eed9c84
      Jeetesh Burman authored 
      

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      4eed9c84
  3. 31 Jan, 2020 1 commit
  5. 07 Feb, 2019 1 commit
  7. 23 Jan, 2019 5 commits
    • Varun Wadekar's avatar
      Tegra186: save system suspend entry marker to TZDRAM · 539c62d7
      Varun Wadekar authored 
      

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra186 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      539c62d7
    • Varun Wadekar's avatar
      Tegra186: helper functions for CPU rst handler and SMMU ctx offset · 889c07c7
      Varun Wadekar authored 
      

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      889c07c7
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Varun Wadekar's avatar
      Tegra186: sanity check target cluster during core power on · b6d1757b
      Varun Wadekar authored 
      

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: Ia73ccf04bd246403de4ffff6e5c99e3b00fb98ca
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b6d1757b
    • Anthony Zhou's avatar
      Tegra186: fix MISRA Rule 8.3 violation · 8dc92783
      Anthony Zhou authored 
      

MISRA Rule 8.3, All declarations of an object or function
shall use the same names and type qualifiers.

This patch removes unused function(s).

Change-Id: I90865c003d46f1dc08bfb5f4fe8a327ea42a2bb7
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      8dc92783
  9. 18 Jan, 2019 3 commits
    • Anthony Zhou's avatar
      Tegra: fix defects flagged by MISRA Rule 10.3 · aa64c5fb
      Anthony Zhou authored 
      

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      aa64c5fb
    • Anthony Zhou's avatar
      Tegra186: fix defects flagged by MISRA scan · 9e7a2436
      Anthony Zhou authored 
      

Main fixes:

Remove unused type conversion

Fix invalid use of function pointer [Rule 1.3]

Fix variable essential type doesn't match [Rule 10.3]

Voided non c-library functions whose return types are not used
 [Rule 17.7]

Change-Id: I23994c9d4d6a240080933d848d2b03865acaa833
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      9e7a2436
    • Varun Wadekar's avatar
      Tegra186: reduce complexity for the 'get_target_pwr_state' handler · 4e1830a9
      Varun Wadekar authored 
      

This patch reduces the code complexity for the platform's 'get_target_pwr_state'
handler, by reducing the number of 'if' conditions and adding helper functions
to calculate power state for the cluster/system.

Tested with 'pmccabe'

Change-Id: I32fa4c814bd97f620f2003fa39f1bfceae563771
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4e1830a9
  11. 16 Jan, 2019 3 commits
  13. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  15. 22 Aug, 2018 1 commit
  17. 14 Jun, 2017 1 commit
  19. 03 May, 2017 1 commit
  21. 01 May, 2017 1 commit
  23. 21 Apr, 2017 1 commit
  25. 07 Apr, 2017 1 commit
  27. 05 Apr, 2017 2 commits
  29. 30 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: implement `get_target_pwr_state` handler · f3a20c32
      Varun Wadekar authored 
      

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.

The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.

Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f3a20c32
  31. 27 Mar, 2017 1 commit
  33. 23 Mar, 2017 5 commits
    • Varun Wadekar's avatar
      Tegra186: reset power state info during CPU_ON · b46ac6dc
      Varun Wadekar authored 
      

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b46ac6dc
    • Varun Wadekar's avatar
      Tegra186: fix programming sequence for SC7/SC8 entry · 50f38a4a
      Varun Wadekar authored 
      

This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power state before querying the MCE firmware to see the
entry to that power state is allowed.

Original change by Allen Yu <alleny@nvidia.com>

Change-Id: I65e03754322188af913fabf41f29d1c3595afd85
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50f38a4a
    • Varun Wadekar's avatar
      Tegra186: program default core wake mask during CPU_SUSPEND · 1b9ab054
      Varun Wadekar authored 
      

This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less SMC
before issuing the actual suspend request.

Original change by Krishna Sitaraman <ksitaraman@nvidia.com>

Change-Id: I1f9351dde4ab30936070e9f42c2882fa691cbe46
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1b9ab054
    • Varun Wadekar's avatar
      Tegra186: clear the system cstate for offline core · c60f58ef
      Varun Wadekar authored 
      

This patch clears the system cstate when offlining a CPU core as we
need to update the sytem cstate to SC7 only when we enter system
suspend.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: I1cff9bbab4db7d390a491c8939aea5db6c6b5c59
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c60f58ef
    • Varun Wadekar's avatar
      Tegra186: save/restore BL31 context to/from TZDRAM · 68c7de6f
      Varun Wadekar authored 
      

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.

In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.

Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      68c7de6f
  35. 22 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
  37. 20 Mar, 2017 9 commits