- 05 Nov, 2019 1 commit
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Roger Lu authored
1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM 2. Switch CLKSQ1/TDCLKSQ control to SPM 3. Switch ck_off/axi_26m control to SPM BUG=b:136980838 TEST=system suspend/resume passed Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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- 03 Oct, 2019 1 commit
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kenny liang authored
Add EMI MPU driver for DRAM protection. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96
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- 16 Sep, 2019 2 commits
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kenny liang authored
Add MTK SPM driver for suspend/resume scenario. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I8207eea95914da9e63c62f3afc8329f3ccd9a22c
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kenny liang authored
Add uart clock gate contol for suspend/resume scenario. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a
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- 10 Sep, 2019 1 commit
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Hung-Te Lin authored
When built for coreboot, we want to enable coreboot library to have better integration. For example, serial console should be initialized by coreboot_serial instead of hard-coded values. Most coreboot configuration will enable memory console, which needs larger XLAT_TABLES so MAX_XLAT_TABLES is increased; and to support that, TZRAM_SIZE also need to be enlarged. Change-Id: I08cf22df2fa26e48284e323d22ad8ce73a6ea803 Signed-off-by: Hung-Te Lin <hungte@chromium.org>
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- 12 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 10 May, 2019 1 commit
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kenny liang authored
- Add basic platform setup - Add generic CPU helper functions - Add delay timer platform implementation - Use TI 16550 uart driver Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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