- 06 Nov, 2019 1 commit
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Jacky Bai authored
Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 05 Nov, 2019 1 commit
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Jacky Bai authored
Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 24 Jul, 2019 1 commit
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Jacky Bai authored
Add the basic support for RDC init/config driver, this module driver can be enhanced more if necessary. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8
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- 17 Jul, 2019 2 commits
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Jun Nie authored
The PicoPi iMX7D is a 2 board development board consisting of a System-on-Module and a carrier baseboard and optimized for the Internet-of-Things (IoT). This patch add basic support to this board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
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Jun Nie authored
For the iMX7 SOCs, part of the code for platform setup implementation can be reused and made common for all these SoCs. This patch extracts the common part for reuse. Signed-off-by: Jun Nie <jun.nie@linaro.org> Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
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- 12 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 04 Jul, 2019 1 commit
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Jacky Bai authored
CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 01 Jul, 2019 1 commit
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Soby Mathew authored
Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
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- 28 Jun, 2019 2 commits
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Ambroise Vincent authored
Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 21 May, 2019 1 commit
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Jacky Bai authored
AIPSTZ provide access control for all the peripherals connected to it. In this patch all the perperals are configured accessible to all the master. it can be customized based the actual use case. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a
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- 20 May, 2019 2 commits
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Leonard Crestez authored
Platform defines are already provided by the build system so let's not duplicate them. Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Leonard Crestez authored
The manual documents that 0x3036006c should contains the soc revision for imx8mq but this always reports A0. Work around this by parsing the ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa. Determining this inside TF-A makes life easier for OS, see for example this linux discussion: https://lkml.org/lkml/2019/5/3/465 The soc revision can also be useful inside TF-A itself, for example for the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas. The clock for OCOTP block can be disabled by OS so only initialize soc revision once at boot time. Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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- 13 May, 2019 1 commit
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Jacky Bai authored
Remove duplicated linker symbols, resue the symbols defined in bl_common.h Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 09 May, 2019 1 commit
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Leonard Crestez authored
The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but it's also applicable to imx8m. This fixes U-Boot not printing commit hash on 8m with upstream TF-A. Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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- 08 May, 2019 2 commits
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Leonard Crestez authored
Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible by 32. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I286b925eead89218cfeddd82f53a634f3447d212
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Leonard Crestez authored
This is similar to imx8mm and allows uboot to run fastboot over USB otg. There is a different set of power domains on 8mq but same bits covers all off them. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d
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- 12 Apr, 2019 1 commit
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 08 Apr, 2019 1 commit
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Jacky Bai authored
The 'drivers/console/aarch64/console.S' is not needed, so remove it from build to fix the build error when 'ERROR_DEPRECATED'set. Change-Id: Id047a355f82fd33298b7e2b49eff289d28eb5b56 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 03 Apr, 2019 2 commits
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Ambroise Vincent authored
Now it is needed to use the full path of the common header files. Commit 09d40e0e ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The old version of the macro is deprecated. Commit cc5859ca ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 13 Mar, 2019 1 commit
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Jacky Bai authored
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 12 Mar, 2019 1 commit
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Jacky Bai authored
for the i.MX8M SOCs, part of the code for gpc and PSCI implementation can be reused and make it common for all these SoCs. this patch extracts the common part for reuse. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 01 Mar, 2019 1 commit
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Anson Huang authored
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 22 Feb, 2019 1 commit
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Chris Spencer authored
For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow the kernel to use the CAAM job rings. This patch sets the master ID of the Cortex A in the JRaMID registers. Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
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- 12 Feb, 2019 1 commit
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Ying-Chun Liu (PaulLiu) authored
This commit migrates to MULTI_CONSOLE_API for IMX Warp7 board. We also rename the functions in imx_uart driver to more specific one. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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- 01 Feb, 2019 1 commit
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Jan, 2019 2 commits
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Anson Huang authored
Current implementation of i.MX8QX power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 24 Jan, 2019 2 commits
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Anson Huang authored
NXP's i.MX8QM uses Cortex-A53 r0p4, enable necessary erratas for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
NXP's i.MX8MQ uses Cortex-A53 r0p4, enable necessary erratas for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 18 Jan, 2019 8 commits
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Bryan O'Donoghue authored
This patch enables Trusted Board Boot for warp7. A subsequent patch contains build/run instructions. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Bryan O'Donoghue authored
This patch defines the expected DTB overlay address in the memory map for this platform. Its important that all points in the boot process agree on this memory map even if not all elements utilize it. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Bryan O'Donoghue authored
Recently upstreamed changes to OP-TEE mean that it is possible for OP-TEE to provide a DTB overlay directly to subsequent boot stages thus negating the requirement to bundle a DTB in the FIP. This patch switches off the dependency on the DTB in the FIP descriptor instead we will provide the necessary data as an overlay from OP-TEE. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Anson Huang authored
This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug. With this function enabled, TF-A's commit hash can be showed in u-boot debug console when booting up, when there is any issue which could be related to TF-A, users can use the commit hash value to easily identify which commit introduces the issue. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
For NXP's i.MX8 SoCs with system controller inside, thermal sensors are maintained by SCFW, Linux needs to call SMC to trap to TF-A for thermal alarm operation etc. by calling SCFW API. This patch adds temperature alarm SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
For NXP's i.MX8 SoCs with system controller inside, OTP is maintained by SCFW, Linux needs to call SMC to trap to TF-A for OTP read/write etc. operations by calling SCFW API. This patch adds OTP SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of misc functions like temperature alarm, dma etc., other Cortex-A clusters can send out command via MU (Message Unit) to system controller for misc operation etc.. This patch adds misc IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
On i.MX8QM/i.MX8QX with system controller inside, the wakeup source is managed in SCFW(system controller firmware), if the wakeup source is belonged to system controller partition, then before Linux suspend, the wakeup source should be set to SC_PM_WAKE_SRC_SCU, and if the wakeup source is belonged to Cortex-A partition, the wakeup source should be set to SC_PM_WAKE_SRC_IRQSTEER, so need to add wakeup source SIP runtime service to get Linux kernel's wakeup source and set the correct wakeup source for system controller. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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