1. 28 Aug, 2020 1 commit
  2. 31 Jul, 2020 1 commit
    • Manish Pandey's avatar
      tbbr/dualroot: rename SP package certificate file · 03a5225c
      Manish Pandey authored
      
      
      Currently only single signing domain is supported for SP packages but
      there is plan to support dual signing domains if CoT is dualroot.
      
      SP_CONTENT_CERT_ID is the certificate file which is currently generated
      and signed with trusted world key which in-turn is derived from Silicon
      provider RoT key.
      To allow dual signing domain for SP packages, other certificate file
      will be derived from Platform owned RoT key.
      
      This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
      does other related changes.
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
      03a5225c
  3. 30 Jul, 2020 2 commits
  4. 10 Jul, 2020 1 commit
  5. 06 Jul, 2020 1 commit
    • Abdellatif El Khlifi's avatar
      corstone700: splitting the platform support into FVP and FPGA · ef93cfa3
      Abdellatif El Khlifi authored
      
      
      This patch performs the following:
      
      - Creating two corstone700 platforms under corstone700 board:
      
        fvp and fpga
      
      - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
      - The platform can be specified using the TARGET_PLATFORM Makefile variable
      (possible values are: fvp or fpga)
      - Allowing to use u-boot by:
        - Enabling NEED_BL33 option
        - Fixing non-secure image base: For no preloaded bl33 we want to
          have the NS base set on shared ram. Setup a memory map region
          for NS in shared map and set the bl33 address in the area.
      - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
      platform
      - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY
      
      Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
      Signed-off-by: default avatarRui Miguel Silva <rui.silva@linaro.org>
      Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      ef93cfa3
  6. 09 Jun, 2020 1 commit
  7. 03 Jun, 2020 2 commits
  8. 27 May, 2020 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce TC0 platform · f5c58af6
      Usama Arif authored
      
      
      This patch adds support for Total Compute (TC0) platform. It is an
      initial port and additional features are expected to be added later.
      
      TC0 has a SCP which brings the primary Cortex-A out of reset
      which starts executing BL1. TF-A optionally authenticates the SCP
      ram-fw available in FIP and makes it available for SCP to copy.
      
      Some of the major features included and tested in this platform
      port include TBBR, PSCI, MHUv2 and DVFS.
      
      Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      f5c58af6
  9. 19 May, 2020 1 commit
    • Alexei Fedorov's avatar
      FVP: Add support for passing platform's topology to DTS · 003faaa5
      Alexei Fedorov authored
      
      
      This patch adds support for passing FVP platform's topology
      configuration to DTS files for compilation, which allows to
      build DTBs with correct number of clusters and CPUs.
      This removes non-existing clusters/CPUs from the compiled
      device tree blob and fixes reported Linux errors when trying
      to power on absent CPUs/PEs.
      If DTS file is passed using FVP_HW_CONFIG_DTS build option from
      the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
      and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
      use the default values from the corresponding DTS file.
      
      Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      003faaa5
  10. 15 May, 2020 1 commit
  11. 17 Apr, 2020 1 commit
  12. 24 Mar, 2020 1 commit
  13. 11 Mar, 2020 1 commit
    • Madhukar Pappireddy's avatar
      fconf: Extract topology node properties from HW_CONFIG dtb · 4682461d
      Madhukar Pappireddy authored
      
      
      Create, register( and implicitly invoke) fconf_populate_topology()
      function which extracts the topology related properties from dtb into
      the newly created fconf based configuration structure 'soc_topology'.
      Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB
      build feature.
      
      A new property which describes the power domain levels is added to the
      HW_CONFIG device tree source files.
      
      This patch also fixes a minor bug in the common device tree file
      fvp-base-gicv3-psci-dynamiq-common.dtsi
      As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary
      to delete all previous cluster node definitons because DynamIQ based
      models have upto 8 CPUs in each cluster. If not deleted, the final dts
      would have an inaccurate description of SoC topology, i.e., cluster0
      with 8 or more core nodes and cluster1 with 4 core nodes.
      
      Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf
      Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      4682461d
  14. 04 Mar, 2020 1 commit
  15. 26 Feb, 2020 1 commit
    • Imre Kis's avatar
      Modify multithreaded dts file of DynamIQ FVPs · e718e61b
      Imre Kis authored
      
      
      The dts file now contains a CPU map that precisely describes the
      topology including thread nodes. The map was also extended to have 16
      PEs to be able to test multithreaded FVPs with 8 cores in the same
      cluster.
      Signed-off-by: default avatarImre Kis <imre.kis@arm.com>
      Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0
      e718e61b
  16. 18 Feb, 2020 1 commit
  17. 17 Feb, 2020 1 commit
  18. 13 Feb, 2020 1 commit
  19. 20 Jan, 2020 2 commits
  20. 14 Jan, 2020 1 commit
    • Balint Dobszay's avatar
      Replace dts includes with C preprocessor syntax · 2d51b55e
      Balint Dobszay authored
      
      
      Using the /include/ syntax, the include was evaluated by dtc, only after running
      the preprocessor, therefore the .dtsi files were not preprocessed. This patch
      adds the #include syntax instead. Evaluating this and preprocessing the files
      now happens in a single step, done by the C preprocessor.
      
      Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0
      Signed-off-by: default avatarBalint Dobszay <balint.dobszay@arm.com>
      2d51b55e
  21. 07 Jan, 2020 1 commit
  22. 18 Dec, 2019 2 commits
  23. 13 Nov, 2019 1 commit
    • Imre Kis's avatar
      Add multithreaded DynamIQ dts file · 38c078e0
      Imre Kis authored
      
      
      The new dts file overrides the MPIDR values of the processing elements
      which were defined in the common dtsi file. The new dts file defines
      four cores in a single cluster, each core having two threads.
      Signed-off-by: default avatarImre Kis <imre.kis@arm.com>
      Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88
      38c078e0
  24. 03 Oct, 2019 1 commit
  25. 23 Sep, 2019 2 commits
    • Usama Arif's avatar
      a5ds: add multicore support · ec885bac
      Usama Arif authored
      
      
      Enable cores 1-3 using psci. On receiving the smc call from kernel,
      core 0 will bring the secondary cores out pen and signal an event for
      the cores. Currently on switching the cores is enabled i.e. it is not
      possible to suspend, switch cores off, etc.
      
      Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      ec885bac
    • Lionel Debieve's avatar
      stm32mp1: add authentication support for stm32image · 4bdb1a7a
      Lionel Debieve authored
      
      
      This commit adds authentication binary support for STM32MP1.
      It prints the bootrom authentication result if signed
      image is used and authenticates the next loaded STM32 images.
      It also enables the dynamic translation table support
      (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.
      Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
      Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
      4bdb1a7a
  26. 08 Sep, 2019 1 commit
    • Imre Kis's avatar
      Add Linux DTS files for 32 bit threaded FVPs · 1946b868
      Imre Kis authored
      
      
      RevC models have the MT bit set and the affinities shifted in the MPIDR
      register. To make the Linux able to boot all CPUs it needs a modified
      DTS file containing the shifted affinity values.
      
      Beside these values the DTS files should be the same so the common part
      was moved into a new file which is included in the DTS files with
      shifted and non-shifted affinities.
      
      The same setup already exists for 64 bit systems.
      Signed-off-by: default avatarImre Kis <imre.kis@arm.com>
      Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d
      1946b868
  27. 20 Aug, 2019 1 commit
    • Manish Pandey's avatar
      plat/arm: Introduce corstone700 platform. · 7bdc4698
      Manish Pandey authored
      
      
      This patch adds support for Corstone-700 foundation IP, which integrates
      both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
      subsystem.
      This is an example implementation of Corstone-700 IP host firmware.
      
      Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
      bringing Host out RESET. Host will start execution directly from BL32 and
      then will jump to Linux.
      
      It is an initial port and additional features are expected to be added
      later.
      
      Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      7bdc4698
  28. 16 Jul, 2019 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce A5 DesignStart platform. · 00c7d5ac
      Usama Arif authored
      
      
      This patch adds support for Cortex-A5 FVP for the
      DesignStart program. DesignStart aims at providing
      low cost and fast access to Arm IP.
      
      Currently with this patch only the primary CPU is booted
      and the rest of them wait for an interrupt.
      Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
      00c7d5ac
  29. 17 Jun, 2019 2 commits
    • Yann Gautier's avatar
      fdts: stm32mp1: realign device tree files with internal devs · f237822f
      Yann Gautier authored
      
      
      Update DDR parameters to version 1.45.
      Remove useless sdmmc1_dir_pins_b node.
      Add USART3 and UART7 nodes.
      Correct a PMIC value for USB regulator.
      Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
      Update DTSI file for SDMMC compatible, but overwrite it with the former
      name.
      Move BSEC board_id node to boards DTS files, as this OTP is specific to
      STMicroelectronics boards.
      
      Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      f237822f
    • Yann Gautier's avatar
      stm32mp1: add general SYSCFG management · f33b2433
      Yann Gautier authored
      
      
      The system configuration controller is mainly used to manage
      the compensation cell and other IOs and system related settings.
      
      The SYSCFG driver is in charge of configuring masters on the interconnect,
      IO compensation, low voltage boards, or pull-ups for boot pins.
      All other configurations should be handled in Linux drivers requiring it.
      
      Device tree files are also updated to manage vdd-supply regulator.
      
      Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42
      Signed-off-by: default avatarNicolas Le Bayon <nicolas.le.bayon@st.com>
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      f33b2433
  30. 26 Apr, 2019 2 commits
  31. 11 Mar, 2019 1 commit
    • Yann Gautier's avatar
      fdts: stm32mp1: add bsec node · 83f62c87
      Yann Gautier authored
      
      
      This node is added in a new file stm32mp157c-security.dtsi.
      This node includes OTPs that should be shadowed and made readable
      to non secure world.
      Explicitly add status and secure-status, as these OTPs are accessible
      by secure and non-secure world.
      
      The stgen node is also moved to this file.
      
      Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      83f62c87
  32. 20 Feb, 2019 1 commit
  33. 19 Feb, 2019 1 commit