- 23 Dec, 2020 1 commit
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Nishanth Menon authored
ARM's generic timer[1] picks up it's graycode from GTC. However, the frequency of the GTC is supposed to be programmed in CNTFID0[2] register. In K3, architecture, GTC provides a central time to many parts of the SoC including graycode to the generic timer in the ARMv8 subsystem. However, due to the central nature and the need to enable the counter early in the boot process, the R5 based bootloader enables GTC and programs it's frequency based on central needs of the system. This may not be a constant 200MHz based on the system. The bootloader is supposed to program the FID0 register with the correct frequency it has sourced for GTC from the central system controller, and TF-A is supposed to use that as the frequency for it's local timer. A mismatch in programmed frequency and what we program for generic timer will, as we can imagine, all kind of weird mayhem. So, check the CNTFID0 register, if it is 0, warn and use the default frequency to continue the boot process. While at it, we can also check CNTCR register to provide some basic diagnostics to make sure that we don't have OS folks scratch their heads. Even though this is used during cpu online operations, the cost of this additional check is minimal enough for us not to use #ifdeffery with DEBUG flags. [1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary [2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0 [3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ib03e06788580f3540dcb1a11677d0d6d398b2c9f
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- 26 Apr, 2019 2 commits
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Andrew F. Davis authored
To make the USE_COHERENT_MEM option work we need to add an entry for the area to our memory map table. Also fixup the alignment here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I1c05477a97646ac73846a711bc38d3746628d847
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Andrew F. Davis authored
The size of the RO data area was calculated by subtracting the area end address from itself and not the base address due to a typo. Fix this here. Note, this was noticed at a glance thanks to the new aligned formating of this table. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7
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- 19 Apr, 2019 4 commits
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Andrew F. Davis authored
This is only a formatting change but makes it instantly clear how each region is set. This is over 80 chars and the MT_RO are not strictly needed but this section very important to get right so make readability the priority here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6
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Andrew F. Davis authored
This should be more secure and looks a bit cleaner. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461
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Andrew F. Davis authored
We don't use this for anything right now, remove it. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66
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Andrew F. Davis authored
This makes definitions more consistent, plus helps alignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc
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- 22 Jan, 2019 1 commit
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Andrew F. Davis authored
Valid addresses for GICR base are always a set calculable distance from the GICD and is based on the number of cores a given instance of GICv3 IP can support. The formula for the number of address bits is given by the ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to one for GICR instances. Holes in the GIC address space are also guaranteed to safely return 0 on reads. This allows us to support runtime detection of the GICR base address by starting from GIC base address plus BIT(18) and walking until the GICR ID register (IIDR) is detected. We stop searching after BIT(20) to prevent searching out into space if something goes wrong. This can be extended out if we ever have a device with 16 or more cores. Signed-off-by: Andrew F. Davis <afd@ti.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 30 Oct, 2018 1 commit
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Andrew F. Davis authored
A recent patch[0] has made setting up page tables into generic code, complete the conversion for TI platforms by removing the use of plat_arm_get_mmap() and using the mmap table directly. [0] 0916c38d ("Convert arm_setup_page_tables into a generic helper") Signed-off-by: Andrew F. Davis <afd@ti.com>
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- 26 Oct, 2018 1 commit
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Roberto Vargas authored
This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. Change-Id: Ie9f149e3fdec935f9329402ed3dd8e1c00b8832c Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 2 commits
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Andrew F. Davis authored
Texas Instrument's System Control Interface (TI-SCI) Message Protocol is used in Texas Instrument's System on Chip (SoC) such as those in K3 family AM654x SoCs to communicate between various compute processors with a central system controller entity. TI-SCI message protocol provides support for management of various hardware entities within the SoC. Add support driver to allow communication with system controller entity within the SoC. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
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Andrew F. Davis authored
Secure Proxy module manages hardware threads that are meant for communication between the processor entities. Add support for this here. Signed-off-by: Andrew F. Davis <afd@ti.com>
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- 24 Jul, 2018 1 commit
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 19 Jun, 2018 6 commits
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Nishanth Menon authored
Do proper initialization of GIC V3. This will allow CP15 access to GIC from "normal world" (aka HLOS) via mrc/mcr calls. K3 SoC family uses GICv3 compliant GIC500 without compatibility for legacy GICv2. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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Nishanth Menon authored
Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC clock is selected statically and override option if the platform has a different configuration. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com>
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Nishanth Menon authored
Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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Nishanth Menon authored
This library will be used to properly set up mappings from different bootloaders at different exception levels. It ensures that memory mapped devices such as UARTs are still accessible and memory regions have the correct access permissions. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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Benjamin Fair authored
Because there is no BL2, BL31 must determine the entrypoint and memory location of BL32 and BL33 on its own. BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board makefile. We also allow a DTB address to be specified for cases when BL33 is a Linux image. NOTE: It is possible to pull in this information from device tree as well, however libfdt does not contain the required hooks to make this happen at this point in time. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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Nishanth Menon authored
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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