- 27 Oct, 2020 3 commits
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Chee Hong Ang authored
Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by:Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by:Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by:
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- 24 Oct, 2020 6 commits
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Abdul Halim, Muhammad Hadi Asyrafi authored
Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: -
Richard Gong authored
Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by:Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c
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Abdul Halim, Muhammad Hadi Asyrafi authored
Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: -
Abdul Halim, Muhammad Hadi Asyrafi authored
Use pre-defined macros for return values and common mailbox arguments Signed-off-by: -
Abdul Halim, Muhammad Hadi Asyrafi authored
Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: -
Chee Hong Ang authored
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by:
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- 19 Aug, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes from commit #1322dc94 . Signed-off-by:
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- 08 Jun, 2020 5 commits
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Tien Hock Loh authored
There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by:Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
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Tien Hock Loh authored
The CCU initialization loop uses the wrong units, this fixes that. This also fixes snoop filter register set bits should be used instead of overwriting the register Signed-off-by: -
Tien Hock Loh authored
FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: -
Tien Hock Loh authored
DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: -
Tien Hock Loh authored
This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by:
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- 27 Feb, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
Modify RSU driver error code for backward-compatibility with Linux RSU driver Signed-off-by:
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- 25 Feb, 2020 3 commits
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch. Revert changing argument type from uint32_t to uint64_t to fix incompatible cast issue. Fix said bug by using intermediate uint32_t array as a more appropriate solution. Signed-off-by: -
Tien Hock, Loh authored
This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by:
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- 20 Feb, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
Fix mailbox driver incompatible cast bug and control flow issue that was flagged by Coverity Scan. Signed-off-by:
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- 07 Feb, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch modify current address range checker in SiP driver to also accept input size. Also, include said checker for SiP mailbox send command to ensure referenced argument is within expected address. Signed-off-by:
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- 05 Feb, 2020 2 commits
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Hadi Asyrafi authored
This update allows normal world to send mailbox commands through SMC Signed-off-by: -
Hadi Asyrafi authored
Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by:
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- 03 Feb, 2020 1 commit
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Hadi Asyrafi authored
Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by:
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- 29 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by:
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by:Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
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- 16 Jan, 2020 7 commits
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Hadi Asyrafi authored
Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: -
Hadi Asyrafi authored
This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: -
Hadi Asyrafi authored
SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or RECONFIG_STATUS based on passed parameter Signed-off-by: -
Hadi Asyrafi authored
Refactored system manager driver to be shared across both intel platform Signed-off-by: -
Hadi Asyrafi authored
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: -
Hadi Asyrafi authored
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: -
Hadi Asyrafi authored
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by:
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- 15 Jan, 2020 2 commits
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Tien Hock, Loh authored
UEFI decompression will fail if the payload size is too large and the load address is too low. This patch moves the payload to a higher address to fix the issue Signed-off-by: -
Hadi Asyrafi authored
All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by:
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- 13 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch removes un-needed r/w parameter checks for qspi driver. The driver can actually access any offset and size. Signed-off-by:
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:
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- 30 Dec, 2019 2 commits
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Hadi Asyrafi authored
Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: -
Hadi Asyrafi authored
Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by:
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