1. 10 Mar, 2020 1 commit
  2. 04 Feb, 2019 1 commit
    • Soby Mathew's avatar
      GICv3: Allow probe for fewer GICR interfaces than exposed by the frame · 5dc2c3f9
      Soby Mathew authored
      
      
      Previously the GICv3 redistributor probe function
      (gicv3_rdistif_base_addrs_probe()) asserted that the number of
      per-CPU redistributor interfaces expected to be probed by the
      platform is equal to the number exported by the redistributor
      frame. This is a problem in case the number of CPUs in the
      platform is less than the number of redistributor interfaces
      in the frame. Hence this patch removes the assertion check
      and allows probe for fewer redistributor interfaces as required
      by the platform.
      
      Change-Id: I3449763a3ad70817224442cbe184d001030c9874
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      5dc2c3f9
  3. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored
      Enforce full include path for includes. Deprecate old paths.
      
      The following folders inside include/lib have been left unchanged:
      
      - include/lib/cpus/${ARCH}
      - include/lib/el3_runtime/${ARCH}
      
      The reason for this change is that having a global namespace for
      includes isn't a good idea. It defeats one of the advantages of having
      folders and it introduces problems that are sometimes subtle (because
      you may not know the header you are actually including if there are two
      of them).
      
      For example, this patch had to be created because two headers were
      called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
      to avoid collision."). More recently, this patch has had similar
      problems: 46f9b2c3 ("drivers: add tzc380 support").
      
      This problem was introduced in commit 4ecca339
      
       ("Move include and
      source files to logical locations"). At that time, there weren't too
      many headers so it wasn't a real issue. However, time has shown that
      this creates problems.
      
      Platforms that want to preserve the way they include headers may add the
      removed paths to PLAT_INCLUDES, but this is discouraged.
      
      Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  4. 28 Sep, 2018 1 commit
  5. 30 Aug, 2018 1 commit
  6. 12 Jun, 2018 1 commit
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.1 · 87d3aacc
      Daniel Boulby authored
      
      
      Rule 5.1: External identifiers shall be distinct
      
      Some of the identifier names in the GICv3 driver were so long that the
      first 31 characters were identical. This patch shortens these names to
      make sure they are different.
      
      Fixed for:
          LOG_LEVEL=50 PLAT=fvp
      
      Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
      Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      87d3aacc
  7. 03 Apr, 2018 1 commit
    • Andre Przywara's avatar
      gicv3: Fix support for systems without secure interrupts · 205cf6e7
      Andre Przywara authored
      
      
      Accessing the interrupt_props array only happens inside a loop over
      interrupt_props_num, so the GICv3 driver can cope with no secure
      interrupts. This allows us to relax the asserts that insists on
      a non-NULL interrupt_props pointer and at least one secure interrupt.
      This enables GICv3 platforms which have no need for a secure interrupt.
      
      This only covers the non-deprecated code paths.
      
      Change-Id: I49db291906512f56af065772f69acb281dfbdcfb
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      205cf6e7
  8. 26 Mar, 2018 1 commit
  9. 13 Nov, 2017 1 commit
    • Jeenu Viswambharan's avatar
      GIC: Fix Group 0 enabling · 385f1dbb
      Jeenu Viswambharan authored
      
      
      At present, the GIC drivers enable Group 0 interrupts only if there are
      Secure SPIs listed in the interrupt properties/list. This means that,
      even if there are Group 0 SGIs/PPIs configured, the group remained
      disabled in the absence of a Group 0 SPI.
      
      Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
      corresponding SGIs/PPIs are present.
      
      Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      385f1dbb
  10. 16 Oct, 2017 5 commits
  11. 03 May, 2017 1 commit
  12. 18 Jul, 2016 1 commit
    • Soby Mathew's avatar
      Rework type usage in Trusted Firmware · 4c0d0390
      Soby Mathew authored
      This patch reworks type usage in generic code, drivers and ARM platform files
      to make it more portable. The major changes done with respect to
      type usage are as listed below:
      
      * Use uintptr_t for storing address instead of uint64_t or unsigned long.
      * Review usage of unsigned long as it can no longer be assumed to be 64 bit.
      * Use u_register_t for register values whose width varies depending on
        whether AArch64 or AArch32.
      * Use generic C types where-ever possible.
      
      In addition to the above changes, this patch also modifies format specifiers
      in print invocations so that they are AArch64/AArch32 agnostic. Only files
      related to upcoming feature development have been reworked.
      
      Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
      4c0d0390
  13. 09 Feb, 2016 2 commits
    • Soby Mathew's avatar
      Move private APIs in gic_common.h to a private header · e9ec3cec
      Soby Mathew authored
      This patch moves the private GIC common accessors from `gic_common.h` to
      a new private header file `gic_common_private.h`. This patch also adds
      additional comments to GIC register accessors to highlight the fact
      that some of them access register values that correspond to multiple
      interrupt IDs. The convention used is that the `set`, `get` and `clr`
      accessors access and modify the values corresponding to a single interrupt
      ID whereas the `read` and `write` GIC register accessors access the raw
      GIC registers and it could correspond to multiple interrupt IDs depending
      on the register accessed.
      
      Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
      e9ec3cec
    • Soby Mathew's avatar
      Fix GIC_IPRIORITYR setting in new drivers · 38a78614
      Soby Mathew authored
      The code to set the interrupt priority for secure interrupts in the
      new GICv2 and GICv3 drivers is incorrect. The setup code to configure
      interrupt priorities of secure interrupts, one interrupt at a time, used
      gicd_write_ipriorityr()/gicr_write_ipriority() function affecting
      4 interrupts at a time. This bug did not manifest itself because all the
      secure interrupts were configured to the highest secure priority(0) during
      cold boot and the adjacent non secure interrupt priority would be configured
      later by the normal world. This patch introduces new accessors,
      gicd_set_ipriorityr() and gicr_set_ipriorityr(), for configuring priority
      one interrupt at a time and fixes the the setup code to use the new
      accessors.
      
      Fixes ARM-software/tf-issues#344
      
      Change-Id: I470fd74d2b7fce7058b55d83f604be05a27e1341
      38a78614
  14. 04 Dec, 2015 1 commit
    • Soby Mathew's avatar
      Rename GICv3 interrupt group macros · 03ffb6bd
      Soby Mathew authored
      This patch renames the GICv3 interrupt group macros from
      INT_TYPE_G0, INT_TYPE_G1S and INT_TYPE_G1NS to INTR_GROUP0,
      INTR_GROUP1S and INTR_GROUP1NS respectively.
      
      Change-Id: I40c66f589ce6234fa42205adcd91f7d6ad8f33d4
      03ffb6bd
  15. 26 Nov, 2015 1 commit
    • Achin Gupta's avatar
      Add ARM GICv3 driver without support for legacy operation · df373737
      Achin Gupta authored
      This patch adds a driver for ARM GICv3 systems that need to run software
      stacks where affinity routing is enabled across all privileged exception
      levels for both security states. This driver is a partial implementation
      of the ARM Generic Interrupt Controller Architecture Specification, GIC
      architecture version 3.0 and version 4.0 (ARM IHI 0069A). The driver does
      not cater for legacy support of interrupts and asymmetric configurations.
      
      The existing GIC driver has been preserved unchanged. The common code for
      GICv2 and GICv3 systems has been refactored into a new file,
      `drivers/arm/gic/common/gic_common.c`. The corresponding header is in
      `include/drivers/arm/gic_common.h`.
      
      The driver interface is implemented in `drivers/arm/gic/v3/gicv3_main.c`.
      The corresponding header is in `include/drivers/arm/gicv3.h`. Helper
      functions are implemented in `drivers/arm/gic/v3/arm_gicv3_helpers.c`
      and are accessible through the `drivers/arm/gic/v3/gicv3_private.h`
      header.
      
      Change-Id: I8c3c834a1d049d05b776b4dcb76b18ccb927444a
      df373737