- 28 Nov, 2019 10 commits
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Steven Kao authored
This patch adds the driver, to implement the programming sequence to save/restore hardware context, during System Suspend/Resume. Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
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Steven Kao authored
This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_* Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39 Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
This patch sanity checks the target cluster value, during core power on, by comparing it against the maximum number of clusters supported by the platform. Reported by: Rohit Khanna <rokhanna@nvidia.com> Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Fix invalid use of function pointer [Rule 1.3] Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Fixed if statement conditional to be essentially boolean [Rule 14.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Krishna Sitaraman authored
This patch updates the wake mask and wake time to indicate to the mce/mts that the cpu is powering down. Wake time is set to highest possible value and wake mask is set to zero. Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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Vignesh Radhakrishnan authored
System suspend sequence involves initializing the SMMU as a part of the system suspend exit, which is currently not present for Tegra194 platform. Thus call tegra_smmu_init() as a part of system suspend exit. Change-Id: I3086301743019e05a40fd221372e7f8713f286ae Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Krishna Sitaraman authored
This patch updates the cpu core id calculation to match with internal numbering method used by the MTS. Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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Vignesh Radhakrishnan authored
Fake system suspend for Tegra194, calls the routine tegra_secure_entrypoint() instead of calling WFI. In essence, this is a debug mode that ensures that the code path of kernel->ATF and back to kernel is executed without depending on other components involved in the system suspend path. This is for ensuring that verification of system suspend can be done on pre-silicon platforms without depending on the rest of the layers being enabled. Change-Id: I18572b169b7ef786f9029600dad9ef5728634f2b Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Varun Wadekar authored
This patch converts the 'target_cpu' and 'target_cluster' variables from the tegra_soc_pwr_domain_on() handler to 32-bits. This fixes the signed comparison warning flagged by the compiler. Change-Id: Idfd7ad2a62749bb0dd032eb9eb5f4b28df32bba0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Krishna Sitaraman authored
This patch adds support for cpu suspend in T19x soc. Change-Id: I8ef1d3e03ee9c528dec34eaff6dcbbfa43941484 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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- 13 Nov, 2019 2 commits
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Vignesh Radhakrishnan authored
- In pre-silicon platforms, MCE might not be ready to support system suspend(SC7) - Thus, in fake system suspend mode, bypass waiting for MCE's acknowledgment to enter system suspend Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6 Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Tejal Kudav authored
This patch does the following: 1. Populate the cstate info corresponding to system suspend and communicate it to the MCE 2. Ask for MCE's acknowledgement for entering system suspend and instruct MCE to get inside system suspend once permitted Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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- 24 Oct, 2019 2 commits
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Steven Kao authored
This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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