- 15 Jun, 2016 1 commit
-
-
Soren Brinkmann authored
Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd UART available in the SoC. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by:
Michal Simek <michal.simek@xilinx.com>
-
- 18 Apr, 2016 1 commit
-
-
Soren Brinkmann authored
Signed-off-by:
-
- 06 Apr, 2016 1 commit
-
-
Soren Brinkmann authored
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by:
-
