- 28 Feb, 2017 2 commits
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Varun Wadekar authored
This patch modifies the secure IRQ registration process to allow platforms to specify the target CPUs as well as the owner of the IRQ. IRQs "owned" by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted OS would return INTR_TYPE_S_EL1 as a result. Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Tegra chips support multiple FIQ interrupt sources. These interrupts are enabled in the GICD/GICC interfaces by the tegra_gic driver. A new FIQ handler would be added in a subsequent change which can be registered by the platform code. This patch adds the GIC programming as part of the tegra_gic_setup() which now takes an array of all the FIQ interrupts to be enabled for the platform. The Tegra132 and Tegra210 platforms right now do not register for any FIQ interrupts themselves, but will definitely use this support in the future. Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Feb, 2017 2 commits
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Varun Wadekar authored
The platform power states, PLAT_MAX_RET_STATE and PLAT_MAX_OFF_STATE, can change on Tegra SoCs and so should be defined per-soc. This patch moves these macro definitions to individual SoC's tegra_def.h files. Change-Id: Ib9b2752bc4d79cef6f79bee49882d340f71977a2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch introduces a function to secure the on-chip TZRAM memory. The Tegra132 and Tegra210 chips do not have a compelling use case to lock the TZRAM. The trusted OS owns the TZRAM aperture on these chips and so it can take care of locking the aperture. This might not be true for future chips and this patch makes the TZRAM programming flexible. Change-Id: I3ac9f1de1b792ccd23d4ded274784bbab2ea224a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 22 Feb, 2017 1 commit
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Varun Wadekar authored
The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Dec, 2015 1 commit
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Varun Wadekar authored
This patch modifies the Tegra port to support the new platform APIs so that we can disable the compat layer. This includes modifications to the power management and platform topology code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Jul, 2015 1 commit
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Varun Wadekar authored
This patch implements support for T132 (Denver CPU) based Tegra platforms. The following features have been added: * SiP calls to switch T132 CPU's AARCH mode * Complete PSCI support, including 'System Suspend' * Platform specific MMIO settings * Locking of CPU vector registers Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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