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  1. 24 Oct, 2019 2 commits
  3. 05 Feb, 2019 1 commit
  5. 31 Jan, 2019 1 commit
  7. 23 Jan, 2019 2 commits
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Anthony Zhou's avatar
      Tegra186: setup: Fix MISRA Rule 8.4 violation · ad67f8c5
      Anthony Zhou authored 
      

MISRA Rule 8.4, A compatible declaration shall be visible when an
object or function with external linkage is defined.

This patch adds static for local array to fix this defect.

Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      ad67f8c5
  9. 16 Jan, 2019 3 commits
  11. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  13. 18 Dec, 2018 1 commit
  15. 28 Sep, 2018 1 commit
  17. 17 Feb, 2018 1 commit
    • Andreas Färber's avatar
      tegra: Fix mmap_region_t struct mismatch · 28db3e96
      Andreas Färber authored 
      Commit fdb1964c

 ("xlat: Introduce
MAP_REGION2() macro") added a granularity field to mmap_region_t.

Tegra platforms were using the v2 xlat_tables implementation in
common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c
where arrays are being defined. This caused the next physical address to
be read as granularity, causing EINVAL error and triggering an assert.

Consistently use xlat_tables_v2.h header to avoid this.

Fixes ARM-software/tf-issues#548.
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      28db3e96
  19. 14 Jun, 2017 1 commit
  21. 03 May, 2017 1 commit
  23. 13 Apr, 2017 1 commit
  25. 07 Apr, 2017 3 commits
    • Varun Wadekar's avatar
      Tegra: allow platforms to override plat_core_pos_by_mpidr() · ae8ac2d2
      Varun Wadekar authored 
      

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ae8ac2d2
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: config to enable SMMU device · 16c7cd01
      Varun Wadekar authored 
      

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but future platforms might not support it.

Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      16c7cd01
    • Varun Wadekar's avatar
      Tegra186: read activity monitor's clock counter values · 691bc22d
      Varun Wadekar authored 
      

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      691bc22d
  27. 30 Mar, 2017 6 commits
  29. 23 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: check MCE firmware version during boot · 5cb89c56
      Varun Wadekar authored 
      

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.

Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5cb89c56
    • Varun Wadekar's avatar
      Tegra186: re-configure MSS' client settings · e64ce3ab
      Varun Wadekar authored 
      

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.

Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e64ce3ab
  31. 22 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
  33. 20 Mar, 2017 5 commits
  35. 28 Feb, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra: GIC: enable FIQ interrupt handling · d3360301
      Varun Wadekar authored 
      

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d3360301
  37. 22 Feb, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra: init normal/crash console for platforms · e1084216
      Varun Wadekar authored 
      

The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e1084216
  39. 20 May, 2016 1 commit
  41. 21 Apr, 2016 1 commit
    • Yatharth Kochar's avatar
      Move `plat_get_syscnt_freq()` to arm_common.c · c073fda1
      Yatharth Kochar authored 
      This patch moves the definition for `plat_get_syscnt_freq()`
from arm_bl31_setup.c to arm_common.c. This could be useful
in case a delay timer needs to be installed based on the
generic timer in other BLs.
This patch also modifies the return type for this function
from `uint64_t` to `unsigned long long` within ARM and other
platform files.

Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
      c073fda1
  43. 04 Dec, 2015 1 commit
  45. 24 Jul, 2015 1 commit
    • Varun Wadekar's avatar
      Tegra: Support for Tegra's T132 platforms · e7d4caa2
      Varun Wadekar authored 
      

This patch implements support for T132 (Denver CPU) based Tegra
platforms.

The following features have been added:

* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e7d4caa2
  47. 29 May, 2015 1 commit
    • Varun Wadekar's avatar
      Support for NVIDIA's Tegra T210 SoCs · 08438e24
      Varun Wadekar authored 
      

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08438e24