- 02 Aug, 2019 2 commits
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Remi Pommarel authored
The CPU[1-3] are reset to initial/cold boot state (with their reset address set to 0x0). In this state the cpus are waiting for another one to set the reset address to bl31_warm_entrypoint and wake them up. The CPU0 needs a bit of a workaround as changing the reset address either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650) does not seem to have any effect. Thus the workaround consists in emulating the other CPUs' behavior with a WFE loop and manually jumping to bl31_warm_entrypoint when woken back up by another one. Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Remi Pommarel authored
Before CPU enters standby state (wfi), the AP needs to signal the SCP through PSCI mailbox. Also at boot time the AP has to wait for the SCP to be ready before sending the first scpi commands or it can crash. Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 16 May, 2019 1 commit
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Kevin Hilman authored
Remove an assert() that assumes a specific value being passed from BL2. This value is dependent on BL2 version, so makes this assert() not portable. Suggested-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Change-Id: Ife3d934b2fa37fc1c66963dd4eb1afe2ca17d740
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- 02 Apr, 2019 4 commits
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Remi Pommarel authored
GXL platforms need to have a specific header at the beginning of bl31 image to be able to boot. This adds a tool to create that and calls it at build time. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Remi Pommarel authored
On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30 and bl301 firmware along with their SHA256 hash over scpi. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Remi Pommarel authored
In order to configure and boot SCP, BL31 has to compute and send the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC has a DMA facility that could be used to offload SHA-256 computations. This adds basic support of this hardware SHA-256 engine. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Antonio Nino Diaz authored
The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested on a lepotato. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Dec, 2018 1 commit
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Julius Werner authored
This patch makes the build system link the console framework code by default, like it already does with other common libraries (e.g. cache helpers). This should not make a difference in practice since TF is linked with --gc-sections, so the linker will garbage collect all functions and data that are not referenced by any other code. Thus, if a platform doesn't want to include console code for size reasons and doesn't make any references to console functions, the code will not be included in the final binary. To avoid compatibility issues with older platform ports, only make this change for the MULTI_CONSOLE_API. Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Oct, 2018 3 commits
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Antonio Nino Diaz authored
There seems to be a problem where SCP can't turn CPU0 off. Instead of returning PSCI_E_DENIED or crashing make CPU0 wait in a WFE loop. This way all CPUs have a consistent behaviour from the point of view of the caller. Change-Id: I5c8c266ca3b69c9e7a4f5ae70afeea5dd36a0825 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This works fine for CPU1-3, but it fails for CPU0, where it is simply ignored and leaves CPU0 in a WFI loop. Change-Id: I7d73683fdd894f2021d6a5bc2cce6cd03e18e633 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The Amlogic Meson S905 is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested in an ODROID-C2. Change-Id: Ia4bc82d7aca42a69d6b118b947279f82b3f6c6da Tested-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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