1. 12 Jun, 2018 2 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.7 Part 2 · a138f768
      Daniel Boulby authored
      
      
      Follow convention of shorter names for smaller scope to fix
      violations of MISRA rule 5.7
      
      To prevent violation of directive 4.5 having variable name channel
      in css_pm_scmi.c not being typographically ambiguous change macro
      argument CHANNEL in css_mhu_doorbell.h change argument to _channel
      to fit with our convention which is a permitted exception of
      directive 4.5 for this project
      
      Rule 5.7: A tag name shall be a unique identifier
      
      Fixed for:
          make LOG_LEVEL=50 PLAT=juno
      
      Change-Id: I147cdb13553e83ed7df19149b282706db115d612
      Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      a138f768
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 5 · ff4e86f9
      Daniel Boulby authored
      
      
      Use a _ prefix for macro arguments to prevent that argument from
      hiding variables of the same name in the outer scope
      
      Rule 5.3: An identifier declared in an inner scope shall not
                hide an identifier declared in an outer scope
      
      Fixed For:
          make LOG_LEVEL=50 PLAT=juno
      
      Change-Id: I575fbc96e8267f2b075e88def1f6e3185394613a
      Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      ff4e86f9
  2. 07 Jun, 2018 1 commit
    • Soby Mathew's avatar
      ARM platforms: Move BL31 below BL2 to enable BL2 overlay · c099cd39
      Soby Mathew authored
      
      
      The patch changes the layout of BL images in memory to enable
      more efficient use of available space. Previously BL31 was loaded
      with the expectation that BL2 memory would be reclaimed by BL32
      loaded in SRAM. But with increasing memory requirements in the
      firmware, we can no longer fit BL32 in SRAM anymore which means the
      BL2 memory is not reclaimed by any runtime image. Positioning BL2
      below BL1-RW and above BL31 means that the BL31 NOBITS can be
      overlaid on BL2 and BL1-RW.
      
      This patch also propogates the same memory layout to BL32 for AArch32
      mode. The reset addresses for the following configurations are also
      changed :
         * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
         * When BL2_AT_EL3=1 for BL2
      
      The restriction on BL31 to be only in DRAM when SPM is enabled
      is now removed with this change. The update to the firmware design
      guide for the BL memory layout is done in the following patch.
      
      Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      c099cd39
  3. 16 Apr, 2018 1 commit
    • Samarth Parikh's avatar
      plat/arm: Add MHUv2 support to SCMI driver · a427785c
      Samarth Parikh authored
      
      
      Currently the SCMI driver supports MHUv1, but Arm platforms may have
      varied versions of MHU driver, with MHUv2 controllers being in the
      latest Arm platforms.
      
      This patch updates the SCMI driver to support MHUv2, specifically that
      the sender must send the wake-up to the receiver before initiating any
      data transfer.
      
      Also, the existing mhu driver files, css_mhu.c and css_mhu.h, have been
      moved from the scpi directory to a new directory, css/drivers/mhu.
      
      Change-Id: I9b46b492a3e1d9e26db12d83a9773958a8c8402f
      Signed-off-by: default avatarSamarth Parikh <samarth.parikh@arm.com>
      a427785c
  4. 13 Apr, 2018 1 commit
  5. 28 Feb, 2018 1 commit
  6. 13 Oct, 2017 2 commits
  7. 06 Sep, 2017 2 commits
    • Soby Mathew's avatar
      CSS: Changes for SDS framework · 18e279eb
      Soby Mathew authored
      
      
      This patch does the required changes to enable CSS platforms
      to build and use the SDS framework. Since SDS is always coupled with
      SCMI protocol, the preexisting SCMI build flag is now renamed to
      `CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
      CSS platforms. Also some of the workarounds applied for SCMI are
      now removed with SDS in place.
      
      Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      18e279eb
    • Soby Mathew's avatar
      SDS: Introduce the sds drivers · 9bedda4a
      Soby Mathew authored
      
      
      This patch introduces the driver for Shared-Data-Structure (SDS)
      framework which will be used for communication between SCP and AP
      CPU. The SDS framework is intended to replace the Boot-Over-MHU
      (BOM) protocol used currently for the communication
      
      Change-Id: Ic174291121f4e581b174cce3389d22d6435f7269
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      9bedda4a
  8. 29 Aug, 2017 1 commit
    • Jeenu Viswambharan's avatar
      plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly · 19583169
      Jeenu Viswambharan authored
      
      
      The current definition of ARM_INSTANTIATE_LOCK macro includes a
      semicolon, which means it's omitted where it's used. This is anomalous
      for a C statement in global scope.
      
      Fix this by removing semicolon from the definition; and where it's a
      NOP, declare a file-scoped variable explicitly tagged as unused to avoid
      compiler warning.
      
      No functional changes.
      
      Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      19583169
  9. 20 Jul, 2017 2 commits
    • Soby Mathew's avatar
      CSS: Prevent SCP_BL2/2U from overwriting BL1 RW data · 1ea63d77
      Soby Mathew authored
      
      
      On ARM CSS platforms, the SCP_BL2/2U image is loaded below
      BL1 read-write data. This same memory is used to load BL31
      later on. But sufficient checks were not done to ensure that the
      SCP_BL2 would not overwrite BL1 rw data. This patch adds the
      required CASSERT checks to prevent overwrite into BL1 or BL2
      memory by load of SCP_BL2/2U. Also the size of BL31 is increased
      and SCP_BL2/2U size is decreased to accomodate it within the
      allocated region.
      
      Change-Id: I23b28b5e1589e91150852a06452bd52b273216ee
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      1ea63d77
    • Soby Mathew's avatar
      CSS: Reorganize the SCP Image transfer functionality · 74d44a49
      Soby Mathew authored
      
      
      The SCP_BL2 is transferred to SCP during BL2 image load and authenticate
      sequence. The Boot-Over-MHU (BOM) protocol is used as transport for this. After
      the SCP boots using the transferred image, the AP CPU waits till the `READY`
      message is received from SCP. This patch separates the API for transport of
      image from the wait for `READY` message and also moves the related files to
      the `css/drivers` folder. The previous API `scp_bootloader_transfer` is
      renamed to `css_scp_boot_image_xfer` to reflect the css naming convention.
      This reorganisation also allows easier switch to a different transport
      (eg: Shared Data Structure based transfer) in future
      
      Change-Id: I8a96f9c4616ffde6dbfdf7c18f6f6f8bfa40bbf0
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      74d44a49
  10. 15 Jun, 2017 1 commit
    • jagadeesh ujja's avatar
      CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set · 878a8bdf
      jagadeesh ujja authored
      
      
      The ARM_PLAT_MT bit enables the support for MT bit in
      MPIDR format. This means that the level 0 affinity
      represents the thread and CPU / Cluster levels are
      at affinity level 1 and 2 respectively.
      This was not catered for in the scpi 'css_scp_get_power_state, API.
      Since the SCPI driver can only cater for single threaded CPUs,
      this patch fixes the problem by catering for this shift by
      effectively ignoring the Thread (level 0) affinity level.
      
      Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe
      Signed-off-by: default avatarjagadeesh ujja <jagadeesh.ujja@arm.com>
      878a8bdf
  11. 09 Jun, 2017 1 commit
  12. 05 Jun, 2017 1 commit
    • Soby Mathew's avatar
      CSS: Add SCMI driver for SCP · c04a3b6c
      Soby Mathew authored
      
      
      This patch adds the SCMI driver for communicating with SCP. The power
      domain management and system power management protocol of the SCMI
      specification[1] is implemented in the driver. The SCP power management
      abstraction layer for SCMI for CSS power management is also added.
      
      A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI
      driver over SCPI.
      
      [1] ARM System Control and Management Interface v1.0 (SCMI)
      Document number: ARM DEN 0056A
      
      Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      c04a3b6c
  13. 03 May, 2017 1 commit
  14. 20 Apr, 2017 1 commit
    • dp-arm's avatar
      css: Ensure PSCI system off/reset is not interrupted · 0498343a
      dp-arm authored
      
      
      If there is a pending interrupt, it is possible for the AP to come out
      of the final WFI before SCP has a chance to act on it.  Prevent this
      by disabling the GIC CPU interface before issuing a WFI.
      
      Previously, SCP would not wait on WFI before taking an action but
      would shut down the core or system regardless.
      
      Change-Id: Ib0bcf69a515d540ed4f73c11e40ec7c863e39c92
      Signed-off-by: default avatardp-arm <dimitris.papastamos@arm.com>
      0498343a
  15. 27 Mar, 2017 1 commit
    • Summer Qin's avatar
      ARM platforms: Add support for MT bit in MPIDR · d8d6cf24
      Summer Qin authored
      
      
      This patch modifies some of the functions in ARM platform layer to cater
      for the case when multi-threading `MT` is set in MPIDR. A new build flag
      `ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR
      now assume that the `MT` bit is set for the platform and access the bit
      fields accordingly.
      
      Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is
      enabled, returning the PE count within the physical cpu corresponding to
      `mpidr`.
      
      Change-Id: I04ccf212ac3054a60882761f4087bae299af13cb
      Signed-off-by: default avatarSummer Qin <summer.qin@arm.com>
      d8d6cf24
  16. 06 Feb, 2017 1 commit
    • Douglas Raillard's avatar
      Replace some memset call by zeromem · 32f0d3c6
      Douglas Raillard authored
      
      
      Replace all use of memset by zeromem when zeroing moderately-sized
      structure by applying the following transformation:
      memset(x, 0, sizeof(x)) => zeromem(x, sizeof(x))
      
      As the Trusted Firmware is compiled with -ffreestanding, it forbids the
      compiler from using __builtin_memset and forces it to generate calls to
      the slow memset implementation. Zeromem is a near drop in replacement
      for this use case, with a more efficient implementation on both AArch32
      and AArch64.
      
      Change-Id: Ia7f3a90e888b96d056881be09f0b4d65b41aa79e
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      32f0d3c6
  17. 07 Dec, 2016 1 commit
    • Soby Mathew's avatar
      Introduce SCP power management abstraction · b12a2b49
      Soby Mathew authored
      
      
      This patch introduces an additional layer of abstraction between
      CSS power management hooks and the SCPI driver. A new set of APIs
      are introduced in order to abstract out power management operations
      from underlying communication mechanism with the SCP.
      
      The SCPI and the associated MHU drivers are moved into a `drivers`
      folder in CSS. The new SCP communication abstraction layer is added
      in the `drivers/scp` folder. The existing CSS power management
      uses the new APIs to reflect this abstraction.
      
      Change-Id: I7d775129fc0558e9703c2724523fb8f0a916838c
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      b12a2b49