1. 20 Apr, 2021 1 commit
    • Mikael Olsson's avatar
      Add SiP service to configure Arm Ethos-N NPU · 76a21174
      Mikael Olsson authored
      
      
      By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
      the non-secure world cannot access the registers needed to use the NPU.
      To still allow the non-secure world to use the NPU, a SiP service has
      been added that can delegate non-secure access to the registers needed
      to use it.
      
      Only the HW_CONFIG for the Arm Juno platform has been updated to include
      the device tree for the NPU and the platform currently only loads the
      HW_CONFIG in AArch64 builds.
      Signed-off-by: default avatarMikael Olsson <mikael.olsson@arm.com>
      Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
      76a21174
  2. 14 Dec, 2020 1 commit
  3. 30 Jul, 2020 1 commit
  4. 07 Feb, 2020 1 commit
    • Vijayenthiran Subramaniam's avatar
      plat/arm/sgi: introduce number of chips macro · 4d37aa76
      Vijayenthiran Subramaniam authored
      
      
      Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
      multi-chip support to define number of chiplets on the platform. By
      default, this flag is set to 1 and does not affect the existing single
      chip platforms.
      
      For multi-chip platforms, override the default value of
      CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
      platform. As an example, the command below sets the number of chiplets
      to two on the RD-N1-Edge multi-chip platform:
      
      export CROSS_COMPILE=<path-to-cross-compiler>
      make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
      
      Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
      Signed-off-by: default avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
      4d37aa76
  5. 06 Feb, 2020 1 commit
    • Max Shvetsov's avatar
      Adds option to read ROTPK from registers for FVP · a6ffddec
      Max Shvetsov authored
      
      
      Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
      Removes hard-coded developer keys. Instead, setting
      ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
      In case of ROT_KEY specified - generates a new hash and replaces the
      original.
      
      Note: Juno board was tested by original feature author and was not tested
      for this patch since we don't have access to the private key. Juno
      implementation was moved to board-specific file without changing
      functionality. It is not known whether byte-swapping is still needed
      for this platform.
      
      Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
      Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      a6ffddec
  6. 27 Nov, 2019 1 commit
    • Paul Beesley's avatar
      doc: Split the User Guide into multiple files · 43f35ef5
      Paul Beesley authored
      
      
      The User Guide document has grown organically over time and
      now covers a wide range of topics, making it difficult to
      skim read and extract information from. Currently, it covers
      these topics and maybe a couple more:
      
      - Requirements (hardware, tools, libs)
      - Checking out the repo
      - Basic build instructions
      - A comprehensive list of build flags
      - FIP packaging
      - Building specifically for Juno
      - Firmware update images
      - EL3 payloads
      - Preloaded BL33 boot flow
      - Running on FVPs
      - Running on Juno
      
      I have separated these out into a few groups that become new
      documents. Broadly speaking, build instructions for the tools,
      for TF-A generally, and for specific scenarios are separated.
      Content relating to specific platforms (Juno and the FVPs are
      Arm-specific platforms, essentially) has been moved into the
      documentation that is specific to those platforms, under
      docs/plat/arm.
      
      Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      43f35ef5