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To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Various changes to comply with MISRA static analysis rules
Signed-off-by: Jolly Shah <jollys@xilinx.com>

Add IOCTLs to read/write global general storage and
persistent global general storage registers access.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

These are empty functions with no logic right now. Code
will be added in subsequent commits.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
  * Set tap delay bypass
  * Set SGMII mode
  * SD reset
  * Set SD/MMC tap delay
Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
  * Get RPU operation mode
  * Set RPU operation mode
  * Configure RPU boot address (OCM/TCM)
  * Configure TCM combined mode
Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>