- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 23 Feb, 2017 1 commit
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Varun Wadekar authored
This patch implements a handler for common SiP calls. A weak implementation for the SoC-specific handler has been provided which can be overridden by SoCs to implement any custom SiP calls. Change-Id: I45122892a84ea35d7b44be0f35dc15f6bb95193e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 22 Feb, 2017 1 commit
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Varun Wadekar authored
This patch converts the common SiP handler to SoC specific SiP handler. T210 and T132 have different SiP SMCs and so it makes sense to move the SiP handler to soc/t132 and soc/t210 folders. Change-Id: Idfe48384d63641137d74a095432df4724986b241 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Jul, 2015 1 commit
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Varun Wadekar authored
This patch implements support for T132 (Denver CPU) based Tegra platforms. The following features have been added: * SiP calls to switch T132 CPU's AARCH mode * Complete PSCI support, including 'System Suspend' * Platform specific MMIO settings * Locking of CPU vector registers Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 12 Jun, 2015 1 commit
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Varun Wadekar authored
This patch adds support to reserve a memory carveout region in the DRAM on Tegra SoCs. The memory controller provides specific registers to specify the aperture's base and size. This aperture can also be changed dynamically in order to re-size the memory available for DRM video playback. In case of the new aperture not overlapping the previous one, the previous aperture has to be cleared before setting up the new one. This means we do not "leak" any video data to the NS world. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 28 Apr, 2015 2 commits
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Sandrine Bailleux authored
The communication protocol used between the AP cores and the SCP in CSS-based platforms like Juno has undergone a number of changes. This patch makes the required modifications to the SCP Boot Protocol, SCPI Protocol and MHU driver code in shared CSS platform code so that the AP cores are still able to communicate with the SCP. This patch focuses on the mandatory changes to make it work. The design of this code needs to be improved but this will come in a subsequent patch. The main changes are: - MHU communication protocol - The command ID and payload size are no longer written into the MHU registers directly. Instead, they are stored in the payload area. The MHU registers are now used only as a doorbell to kick off messages. Same goes for any command result, the AP has to pick it up from the payload area. - SCP Boot Protocol - The BL3-0 image is now expected to embed a checksum. This checksum must be passed to the SCP, which uses it to check the integrity of the image it received. - The BL3-0 image used to be transferred a block (4KB) at a time. The SCP now supports receiving up to 128KB at a time, which is more than the size of the BL3-0 image. Therefore, the image is now sent in one go. - The command IDs have changed. - SCPI Protocol - The size of the SCPI payload has been reduced down from 512 bytes to 256 bytes. This changes the base address of the AP-to-SCP payload area. - For commands that have a response, the response is the same SCPI header that was sent, except for the size and the status, which both must be updated appropriately. Success/Failure of a command is determined by looking at the updated status code. - Some command IDs have changed. NOTE: THIS PATCH BREAKS COMPATIBILITY WITH FORMER VERSIONS OF THE SCP FIRMWARE AND THUS REQUIRES AN UPDATE OF THIS BINARY. THE LATEST SCP BINARY CAN BE OBTAINED FROM THE ARM CONNECTED COMMUNITY WEBSITE. Change-Id: Ia5f6b95fe32401ee04a3805035748e8ef6718da7
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Dan Handley authored
This major change pulls out the common functionality from the FVP and Juno platform ports into the following categories: * (include/)plat/common. Common platform porting functionality that typically may be used by all platforms. * (include/)plat/arm/common. Common platform porting functionality that may be used by all ARM standard platforms. This includes all ARM development platforms like FVP and Juno but may also include non-ARM-owned platforms. * (include/)plat/arm/board/common. Common platform porting functionality for ARM development platforms at the board (off SoC) level. * (include/)plat/arm/css/common. Common platform porting functionality at the ARM Compute SubSystem (CSS) level. Juno is an example of a CSS-based platform. * (include/)plat/arm/soc/common. Common platform porting functionality at the ARM SoC level, which is not already defined at the ARM CSS level. No guarantees are made about the backward compatibility of functionality provided in (include/)plat/arm. Also remove any unnecessary variation between the ARM development platform ports, including: * Unify the way BL2 passes `bl31_params_t` to BL3-1. Use the Juno implementation, which copies the information from BL2 memory instead of expecting it to persist in shared memory. * Unify the TZC configuration. There is no need to add a region for SCP in Juno; it's enough to simply not allow any access to this reserved region. Also set region 0 to provide no access by default instead of assuming this is the case. * Unify the number of memory map regions required for ARM development platforms, although the actual ranges mapped for each platform may be different. For the FVP port, this reduces the mapped peripheral address space. These latter changes will only be observed when the platform ports are migrated to use the new common platform code in subsequent patches. Change-Id: Id9c269dd3dc6e74533d0e5116fdd826d53946dc8
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- 19 Aug, 2014 1 commit
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Dan Handley authored
* Move TSP platform porting functions to new file: include/bl32/tsp/platform_tsp.h. * Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic TSP interrupt handling code, instead of depending on the FVP specific definition IRQ_SEC_PHY_TIMER. * Rename TSP platform porting functions from bl32_* to tsp_*, and definitions from BL32_* to TSP_*. * Update generic TSP code to use new platform porting function names and definitions. * Update FVP port accordingly and move all TSP source files to: plat/fvp/tsp/. * Update porting guide with above changes. Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO BE UPDATED Fixes ARM-software/tf-issues#167 Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
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- 06 May, 2014 1 commit
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Dan Handley authored
Reduce the number of header files included from other header files as much as possible without splitting the files. Use forward declarations where possible. This allows removal of some unnecessary "#ifndef __ASSEMBLY__" statements. Also, review the .c and .S files for which header files really need including and reorder the #include statements alphabetically. Fixes ARM-software/tf-issues#31 Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
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- 17 Jan, 2014 1 commit
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Dan Handley authored
Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60
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- 05 Dec, 2013 1 commit
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Dan Handley authored
- Add instructions for contributing to ARM Trusted Firmware. - Update copyright text in all files to acknowledge contributors. Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
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- 25 Oct, 2013 1 commit
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Achin Gupta authored
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