- 19 Jun, 2018 3 commits
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Benjamin Fair authored
These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by:
Benjamin Fair <b-fair@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
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Benjamin Fair authored
The K3 family of SoCs has multiple interconnects. The key interconnect for high performance processors is the MSMC3 interconnect. This is an io-coherent interconnect which exports multiple ports for each processor cluster. Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated such that the instance of ATF does not manage it. Define macros in platform_def.h to help handle this. Signed-off-by:
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Nishanth Menon authored
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by:
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