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  1. 11 May, 2020 2 commits
    • Etienne Carriere's avatar
      drivers: stm32mp1 clocks: support shifted clock selector bit masks · 8ae08dcd
      Etienne Carriere authored 
      

The current implementation optimizes memory consumed by gateable
clock table by storing bit mask and bit shift with 1 byte each.
The issue is that register selector bit masks above the 7th LSBit
cannot be stored.

This change uses the shift info to shift the mask before it is used,
allowing clock selector register bit fields to be spread on the 32 bits
of the register as long as the mask fits in 8 contiguous bit at most.

This change is needed to add the RTC clock to the gateable clocks table.

Change-Id: I8a0fbcbf20ea383fb3d712f5064d2d307e44465d
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      8ae08dcd
    • Etienne Carriere's avatar
      drivers: stm32mp1 clocks: allow tree lookup for several system clocks · 8fbcd9e4
      Etienne Carriere authored 
      

Oscillators, PLLs and some system clocks can be related straight to
a parent clock. Prior this change were only oscillators and few
clocks supported by this look up. This changes adds PLLs and other
system clocks. This enables for flexible use of clock tree exploration
when computing a clock frequency value.

Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      8fbcd9e4
  3. 05 May, 2020 1 commit
    • Andre Przywara's avatar
      plat/stm32: Use generic fdt_get_reg_props_by_name() · 7ad6d362
      Andre Przywara authored 
      

The STM32 platform port parse DT nodes to find base address to
peripherals. It does this by using its own implementation, even though
this functionality is generic and actually widely useful outside of the
STM32 code.

Re-implement fdt_get_reg_props_by_name() on top of the newly introduced
fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c.
This is removes the assumption that #address-cells and #size-cells are
always one.

Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      7ad6d362
  5. 29 Apr, 2020 1 commit
    • Andre Przywara's avatar
      plat/stm32: Implement fdt_read_uint32_default() as a wrapper · be858cff
      Andre Przywara authored 
      

The STM32 platform code uses its own set of FDT helper functions,
although some of them are fairly generic.

Remove the implementation of fdt_read_uint32_default() and implement it
on top of the newly introduced fdt_read_uint32() function, then convert
all users over.

This also fixes two callers, which were slightly abusing the "default"
semantic.

Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      be858cff
  7. 28 Apr, 2020 1 commit
    • Andre Przywara's avatar
      plat/stm32: Use generic fdt_read_uint32_array() implementation · 52a616b4
      Andre Przywara authored 
      

The device tree parsing code for the STM32 platform is using its own FDT
helper functions, some of them being rather generic.
In particular the existing fdt_read_uint32_array() implementation is now
almost identical to the new generic code in fdt_wrappers.c, so we can
remove the ST specific version and adjust the existing callers.

Compared to the original ST implementation the new version takes a
pointer to the DTB as the first argument, and also swaps the order of
the number of cells and the pointer.

Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      52a616b4
  9. 26 Mar, 2020 1 commit
    • Yann Gautier's avatar
      stm32mp1: dynamically map DDR later and non-cacheable during its test · 84686ba3
      Yann Gautier authored 
      

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      84686ba3
  11. 23 Mar, 2020 3 commits
  13. 25 Feb, 2020 1 commit
  15. 20 Jan, 2020 2 commits
  17. 10 Jan, 2020 1 commit
  19. 03 Oct, 2019 1 commit
  21. 23 Sep, 2019 1 commit
    • Lionel Debieve's avatar
      stm32mp1: add authentication support for stm32image · 4bdb1a7a
      Lionel Debieve authored 
      

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.
Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
      4bdb1a7a
  23. 20 Sep, 2019 2 commits
  25. 10 Sep, 2019 1 commit
  27. 02 Sep, 2019 7 commits
  29. 17 Jun, 2019 5 commits
  31. 03 Apr, 2019 1 commit
  33. 08 Mar, 2019 1 commit
  35. 20 Feb, 2019 1 commit
  37. 14 Feb, 2019 7 commits