- 19 Nov, 2020 1 commit
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Pali Rohár authored
This new target builds boot-image.bin binary as described in documentation. This image does not contain WTMI image and therefore WTP repository is not required for building. Having ability to build just this boot-image.bin binary without full flash-image.bin is useful for A3720 Turris MOX board which does not use Marvell's WTP and a3700_utils. To reduce duplicity between a8k and a3k code, define this new target and also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file marvell_common.mk. For this purpose it is needed to include plat/marvell/marvell.mk file from a3700_common.mk unconditionally (and not only when WTP is defined). Now when common file plat/marvell/marvell.mk does not contain definition for building $(DOIMAGETOOL), it is possible to move its inclusion at the top of the a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
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- 21 Oct, 2020 1 commit
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Pali Rohár authored
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
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- 19 Oct, 2020 1 commit
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Pali Rohár authored
Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa
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- 04 Oct, 2020 3 commits
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Grzegorz Jaszczyk authored
The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Stefan Chulski authored
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 30 Jul, 2020 5 commits
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Alex Evraev authored
As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Grzegorz Jaszczyk authored
Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Ben Peled authored
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
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Alex Evraev authored
Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Moti Buskila authored
the twin-die combined memory device should be treated as X8 device and not as X16 one. This patch is required to re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade. Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97 Signed-off-by: Moti Buskila <motib@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 10 Jul, 2020 4 commits
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Grzegorz Jaszczyk authored
There is no need to open tree different IO window when there is possibility of having one covering required range. Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Konstantin Porotchkin authored
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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- 03 Jul, 2020 2 commits
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Luka Kovacic authored
Add support for the iEi Puzzle-M801 board that is based on the Marvell Armada 88F8040 SoC. It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC). The iEi Puzzle-M801 board is using a custom MCU to handle board power management. The MCU is managing the boards power LEDs, fans and some other periferals. It's using UART for communication. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8
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Luka Kovacic authored
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for determening the path of the system_power.c file. The variable was not updated, when it was deprecated in a8k_common.mk in commit 613bbde0 . Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8
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- 19 Jun, 2020 9 commits
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Konstantin Porotchkin authored
Adjust the latest OP-TEE memory definitions to the newest TF-A baseline. Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Extend the CCU tables with secure SRAM window in all board setups that uses SoCs based on AP806/AP807 North Bridges Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Marcin Wojtas authored
It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
- Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Ben Peled authored
The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com>
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Konstantin Porotchkin authored
As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Grzegorz Jaszczyk authored
The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Before this patch the configuration took place only for CP0 and CP1, but since new platforms can contains up to 3 CPs update is required. Change-Id: Iebd50bbe7b9772063e2c4efb3a7ecbfd593e950d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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- 06 Jun, 2020 11 commits
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Alex Leibovich authored
Change a topology map from internal database to SPD based for 32bit bus width mode Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72 Signed-off-by: Alex Leibovich <alexl@marvell.com>
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Alex Leibovich authored
Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com>
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Alex Leibovich authored
This commit introduces 32-bit DDR topology map initialization. For that purpose a new DDR32 build flag is added, with according documentation update. Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01 Signed-off-by: Alex Leibovich <alexl@marvell.com>
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Grzegorz Jaszczyk authored
This commit introduces two changes: - remove hardcoded references to mci0 from the driver - perform mci optimization for all mci interfaces It fixes performance issues observed on cn9132 CP2. Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
The mci_initialize function name was misleading. The function itself doesn't initialize MCI in general but performs MCI link tuning for performance improvement. Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Change-Id: Id702c070c433f8439faad115830e71b2873ab70a Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Snoop filter needs to be enabled once per cluster. Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
By default all external CPs start with configuration address space set to 0xf200_0000. To overcome this issue, go in the loop and initialize the CP one by one, using temporary window configuration which allows to access each CP and update its configuration space according to decoding windows scheme defined for each platform. In case of cn9130 after this procedure bellow addresses will be used: CP0 - f2000000 CP1 - f4000000 CP2 - f6000000 When the re-configuration is done there is need to restore previous decoding window configuration(init_io_win). Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
As a preparation for upcoming support for CN9130 platform, which is classified as OcteonTx2 product but inherits functionality from a8k, allow to use a8k_common.mk and mss_common.mk from outside of PLAT_FAMILY_BASE. Above is done by introducing BOARD_DIR which needs to be set by each platform, before including a8k_common.mk and mss_common.mk. This will allow to use mentioned mk files not only for platforms located under previously defined PLAT_FAMILY_BASE. Change-Id: I22356c99bc0419a40ae11e42f37acd50943ea134 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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