1. 25 Mar, 2021 2 commits
    • Andre Przywara's avatar
      allwinner: Move sunxi_cpu_power_off_self() into platforms · 9227719d
      Andre Przywara authored
      
      
      The code to power the current core off when SCPI is not available is now
      different for the two supported SoC families.
      To make adding new platforms easier, move sunxi_cpu_power_off_self()
      into the SoC directory, so we don't need to carry definitions for both
      methods for all SoCs.
      
      On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
      of all the code to program the ARISC, which is now only needed for the
      A64 version.
      
      Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      9227719d
    • Andre Przywara's avatar
      allwinner: Move SEPARATE_NOBITS_REGION to platforms · eb15bdaa
      Andre Przywara authored
      
      
      For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
      some parts of the data into separate memory regions (to save on the SRAM
      A2 we are loaded into).
      For the upcoming H616 platform this is of no concern (we run in DRAM),
      so make this flag a platform choice instead.
      
      Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      eb15bdaa
  2. 23 Mar, 2021 1 commit
  3. 24 Jan, 2021 9 commits
    • Andre Przywara's avatar
      allwinner: Allow conditional compilation of SCPI and native PSCI ops · b23ab8eb
      Andre Przywara authored
      
      
      Now that we have split the native and the SCPI version of the PSCI ops,
      we can introduce build options to compile in either or both of them.
      
      If one version is not compiled in, some stub functions make sure the
      common code still compiles and makes the right decisions.
      
      By default both version are enabled (as before), but one of them can be
      disabled on the make command line, or via a platform specific Makefile.
      
      Change-Id: I0c019d8700c0208365eacf57809fb8bc608eb9c0
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      b23ab8eb
    • Samuel Holland's avatar
      allwinner: Split native and SCPI-based PSCI implementations · fe753c97
      Samuel Holland authored
      
      
      In order to keep SCP firmware as optional, the original, limited native
      PSCI implementation was kept around as a fallback. This turned out to be
      a good decision, as some newer SoCs omit the ARISC, and thus cannot run
      SCP firmware.
      
      However, keeping the two implementations in one file makes things
      unnecessarily messy. First, it is difficult to compile out the
      SCPI-based implementation where it is not applicable. Second the check
      is done in each callback, while scpi_available is only updated at boot.
      This makes the individual callbacks unnecessarily complicated.
      
      It is cleaner to provide two entirely separate implementations in two
      separate files. The native implementation does not support any kind of
      CPU suspend, so its callbacks are greatly simplified. One function,
      sunxi_validate_ns_entrypoint, is shared between the two implementations.
      
      Finally, the logic for choosing between implementations is kept in a
      third file, to provide for platforms where only one implementation is
      applicable and the other is compiled out.
      
      Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      fe753c97
    • Samuel Holland's avatar
      allwinner: psci: Improve system shutdown/reset sequence · dae98b3a
      Samuel Holland authored
      
      
      - When the SCPI shutdown/reset command returns success, the SCP is
        still waiting for the CPU to enter WFI. Do that.
      - Peform board-level poweroff before CPU poweroff. If there is a PMIC
        available, it will turn everything off including the CPUs, so doing
        CPU poweroff first is a waste of cycles.
      - During poweroff, attempt to turn off the local CPU using the ARISC.
        This should use slightly less power than just an infinite WFI.
      - Drop the WFI in the reset failure path. The panic will hang anyway.
      
      Change-Id: I897efecb3fe4e77a56041b97dd273156ec51ef8e
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      dae98b3a
    • Samuel Holland's avatar
      allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback · 975d076d
      Samuel Holland authored
      
      
      When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
      the ARISC to perform the power-off process; the SCP waits for the CPU to
      enter WFI before acutally powering it off. Since this matches the
      expected split between .pwr_domain_off and .pwr_domain_pwr_down_wfi, we
      can move the sunxi_cpu_power_off_self() call to sunxi_pwr_domain_off().
      Since that change makes sunxi_pwr_down_wfi() equivalent to the default
      implementation, the callback is no longer needed.
      
      Change-Id: I7d65f66c550d1c69fa5e9945affd7a25b3d3ef42
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      975d076d
    • Samuel Holland's avatar
      allwinner: Separate code to power off self and other CPUs · a1d349be
      Samuel Holland authored
      
      
      Currently, sunxi_cpu_off() has two separate code paths: one for the
      local CPU, and one for other CPUs. Let's split them in to two functions.
      This actually simplifies things, because all callers either operate on
      the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
      (sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
      to choose the appropriate code path.
      
      Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      a1d349be
    • Samuel Holland's avatar
      allwinner: Leave CPU power alone during BL31 setup · ed267c92
      Samuel Holland authored
      
      
      Disabling secondary CPUs during boot is unnecessary because the other
      CPUs are already in reset, and it saves an entirely insignificant amount
      of power. Let's remove this bit of code that was added mostly "because
      we can", and along with it remove an unconditional dependency on the CPU
      ops functions.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7
      ed267c92
    • Samuel Holland's avatar
      allwinner: psci: Invert check in .validate_ns_entrypoint · 814dce8f
      Samuel Holland authored
      
      
      Checking the exceptional case and letting the success case fall through
      is not only more idiomatic, but it also allows adding more exceptional
      cases in the future, such as a check for overlapping secure DRAM.
      
      Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      814dce8f
    • Samuel Holland's avatar
      allwinner: psci: Drop MPIDR check from .pwr_domain_on · 772ef7e7
      Samuel Holland authored
      
      
      This duplicated the logic in psci_validate_mpidr() which was already
      called from psci_cpu_on().
      
      Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      772ef7e7
    • Samuel Holland's avatar
      allwinner: psci: Drop .get_node_hw_state callback · a1473c99
      Samuel Holland authored
      
      
      This optional PSCI function was only implemented when SCPI was
      available. However, the underlying SCPI function is not able to fulfill
      the necessary contract. First, the SCPI protocol has no way to represent
      HW_STANDBY at the CPU power level. Second, the SCPI implementation
      maintains its own logical view of power states, and its implementation
      of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
      Thus it cannot provide "the physical view of power state", as required
      for this function by the PSCI specification.
      
      Since the function is optional, drop it.
      
      Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      a1473c99
  4. 14 Dec, 2020 5 commits
  5. 17 Aug, 2020 1 commit
  6. 29 Jun, 2020 1 commit
  7. 25 Feb, 2020 1 commit
  8. 13 Feb, 2020 4 commits
    • Samuel Holland's avatar
      allwinner: Implement PSCI system suspend using SCPI · e382c88e
      Samuel Holland authored
      
      
      If an SCP firmware is present and able to communicate via SCPI, then use
      that to implement CPU and system power state transitions, including CPU
      hotplug and system suspend. Otherwise, fall back to the existing CPU
      power control implementation.
      
      The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
      SCPI shared memory is at the very end of this region (and therefore the
      end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
      (not counting the ARISC exception vector area) and fills up to the
      beginning of the SCP firmware.
      
      Because the SCP firmware is not loaded adjacent to the ARISC exception
      vector area, the jump instructions used for exception handling cannot be
      included in the SCP firmware image, and must be initialized here before
      turning on the SCP.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c
      e382c88e
    • Samuel Holland's avatar
      allwinner: Add a msgbox driver for use with SCPI · 50cabf6d
      Samuel Holland authored
      
      
      The function names follow the naming convention used by the existing
      ARM SCPI client.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48
      50cabf6d
    • Samuel Holland's avatar
      allwinner: Reserve and map space for the SCP firmware · 57b36632
      Samuel Holland authored
      
      
      The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
      the SCPI shared memory area, which must be mapped as MT_DEVICE to
      prevent problems with cache coherency between the AP CPUs and the SCP.
      For simplicity, map the whole SCP region as MT_DEVICE.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8
      57b36632
    • Samuel Holland's avatar
      allwinner: Adjust SRAM A2 base to include the ARISC vectors · ae3fe6e3
      Samuel Holland authored
      
      
      The ARISC vector area consists of 0x4000 bytes before the beginning of
      usable SRAM. Still, it is technically a part of SRAM A2, so include it
      in the memory definition. This avoids the confusing practice of
      subtracting from the beginning of the SRAM region when referencing the
      ARISC vectors.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf
      ae3fe6e3
  9. 24 Jan, 2020 1 commit
  10. 20 Jan, 2020 1 commit
    • Samuel Holland's avatar
      allwinner: Clean up MMU setup · ddb4c9e0
      Samuel Holland authored
      
      
      Remove the general BL31 mmap region: it duplicates the existing static
      mapping for the entire SRAM region. Use the helper definitions when
      applicable to simplify the code and add the MT_EXECUTE_NEVER flag.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
      ddb4c9e0
  11. 15 Jan, 2020 1 commit
    • Samuel Holland's avatar
      allwinner: Reenable USE_COHERENT_MEM · 6c281cc3
      Samuel Holland authored
      
      
      Now that there is plenty of space (32 KiB) available for NOBITS
      sections, we can afford using an entire page for coherent memory. In
      fact, because it simplifies the code, this is a beneficial change for
      loaded image (.text) size, where we are still close to the size limit.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
      6c281cc3
  12. 29 Dec, 2019 2 commits
  13. 14 Dec, 2019 3 commits
  14. 04 Dec, 2019 1 commit
  15. 28 Jun, 2019 1 commit
  16. 08 Jun, 2019 1 commit
    • Samuel Holland's avatar
      allwinner: Disable unused features to save space · 8f31853b
      Samuel Holland authored
      
      
      As all Allwinner platforms are single-cluster A53 chips, we can disable
      support for newer, unsupported architecture extensions. We can also
      avoid some cache maintenance code, since no platform-specific setup is
      required to enable coherency.
      
      These changes reduce the size of .text on a default build with GCC 9.1
      enough that .vectors again fits in the second half of a page, instead
      of requiring its own page.
      
      This commit was boot-tested on the Pinebook.
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d
      8f31853b
  17. 10 Apr, 2019 1 commit
  18. 18 Feb, 2019 2 commits
  19. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored
      Enforce full include path for includes. Deprecate old paths.
      
      The following folders inside include/lib have been left unchanged:
      
      - include/lib/cpus/${ARCH}
      - include/lib/el3_runtime/${ARCH}
      
      The reason for this change is that having a global namespace for
      includes isn't a good idea. It defeats one of the advantages of having
      folders and it introduces problems that are sometimes subtle (because
      you may not know the header you are actually including if there are two
      of them).
      
      For example, this patch had to be created because two headers were
      called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
      to avoid collision."). More recently, this patch has had similar
      problems: 46f9b2c3 ("drivers: add tzc380 support").
      
      This problem was introduced in commit 4ecca339
      
       ("Move include and
      source files to logical locations"). At that time, there weren't too
      many headers so it wasn't a real issue. However, time has shown that
      this creates problems.
      
      Platforms that want to preserve the way they include headers may add the
      removed paths to PLAT_INCLUDES, but this is discouraged.
      
      Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  20. 07 Dec, 2018 1 commit
    • Julius Werner's avatar
      drivers/console: Link console framework code by default · 985ee0b7
      Julius Werner authored
      
      
      This patch makes the build system link the console framework code by
      default, like it already does with other common libraries (e.g. cache
      helpers). This should not make a difference in practice since TF is
      linked with --gc-sections, so the linker will garbage collect all
      functions and data that are not referenced by any other code. Thus, if a
      platform doesn't want to include console code for size reasons and
      doesn't make any references to console functions, the code will not be
      included in the final binary.
      
      To avoid compatibility issues with older platform ports, only make this
      change for the MULTI_CONSOLE_API.
      
      Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      985ee0b7