- 02 Apr, 2019 3 commits
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Antonio Nino Diaz authored
The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested on a lepotato. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Marek Vasut authored
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM bank size in MiB instead of GiB in case the bank size is smaller than 1 GiB. This prevents printing zeroes on systems with small DRAM sizes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 01 Apr, 2019 2 commits
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Ambroise Vincent authored
Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Mar, 2019 1 commit
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Marek Vasut authored
The M3W ULCB board has 2 GiB of DRAM, set it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 21 Mar, 2019 2 commits
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John Tsichritzis authored
Fixed the below bugs: 1) Bug related to build flag V=1: if the flag was V=0, building with ROMLIB would fail. 2) Due to a syntax bug in genwrappers.sh, index file entries marked as "patch" or "reserved" were ignored. 3) Added a prepending hash to constants that genwrappers is generating. 4) Due to broken dependencies, currently the inclusion functionality is intentionally not utilised. This is why the contents of romlib/jmptbl.i have been copied to platform specific jmptbl.i files. As a result of the broken dependencies, when changing the index files, e.g. patching functions, a clean build is always required. This is a known issue that will be fixed in the future. Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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- 14 Mar, 2019 4 commits
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Heiko Stuebner authored
The Rockchip ATF platform can be entered from both Coreboot and U-Boot. While Coreboot does submit the list of linked parameter structs as platform param, upstream u-boot actually always provides a pointer to a devicetree as parameter. This results in current ATF not running at all when started from U-Boot. To fix this, add a stub that checks if the parameter is a fdt so we can at least boot and not get stuck. Later on we can extend this with actual parsing of information from the devicetree. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Louis Mayencourt authored
When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init section. This is by default enable on FVP. Due to the size increase of the .text.init section, the stack had to be adjusted contain it. Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Sandrine Bailleux authored
The dummy implementation of the plat_init_apiakey() platform API uses an internal 128-bit buffer to store the initial key value used for Pointer Authentication support. The intent - as stated in the file comments - was for this buffer to be write-protected by the MMU. Initialization of the buffer would be performed before enabling the MMU, thus bypassing write protection checks. However, the key buffer ended up into its own read-write section by mistake due to a typo on the section name ('rodata.apiakey' instead of '.rodata.apiakey', note the leading dot). As a result, the linker script was not pulling it into the .rodata output section. One way to address this issue could have been to fix the section name. However, this approach does not work well for BL1. Being the first image in the boot flow, it typically is sitting in real ROM so we don't have the capacity to update the key buffer at any time. The dummy implementation of plat_init_apiakey() provided at the moment is just there to demonstrate the Pointer Authentication feature in action. Proper key management and key generation would have to be a lot more careful on a production system. Therefore, the approach chosen here to leave the key buffer in writable memory but move it to the BSS section. This does mean that the key buffer could be maliciously updated for intalling unintended keys on the warm boot path but at the feature is only at an experimental stage right now, this is deemed acceptable. Change-Id: I121ccf35fe7bc86c73275a4586b32d4bc14698d6 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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John Tsichritzis authored
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 13 Mar, 2019 5 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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Jacky Bai authored
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Muhammad Hadi Asyrafi Abdul Halim authored
To support the enablement of QSPI booting Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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Masahisa Kojima authored
MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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Masahisa Kojima authored
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 12 Mar, 2019 1 commit
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Jacky Bai authored
for the i.MX8M SOCs, part of the code for gpc and PSCI implementation can be reused and make it common for all these SoCs. this patch extracts the common part for reuse. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 08 Mar, 2019 4 commits
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Andre Przywara authored
So far the DT node describing the AXP803 PMIC used in many Allwinner A64 boards had only one subnode, so our code just entering the first subnode to find all regulators worked fine. However recent DT updates in the Linux kernel add more subnodes *before* that, so we need to make sure to explicitly enter the "regulators" subnode to find the information we are after. Improve some DT node parsing error handling on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Luca Ceresoli authored
Allow EL2 (e.g. U-Boot) to load the configuration object at runtime into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot and U-Boot SPL with PMU FW without hard-coding the configuration object. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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- 07 Mar, 2019 3 commits
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Yann Gautier authored
The change of the structure highlighted the fact that all fields are not correctly initialized with zeroes. Replace the other memset in the function with zeromem, as it is faster. Change-Id: I27f45a64e34637f79fa519f486bf5936721ef396 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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Tien Hock, Loh authored
We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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- 04 Mar, 2019 1 commit
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Marek Vasut authored
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 01 Mar, 2019 2 commits
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Varun Wadekar authored
This patch provides dummy macros and platform files to compile the io_storage driver backend. This patch is necessary to remove the "--unresolved=el3_panic" linker flag from Tegra's makefiles and allow us to revert this workaround, previously suggested by the ARM toolchain team. The "--unresolved=el3_panic" flag actually was a big hammer that allowed Tegra platforms to work with armlink previously but it masks legit errors with the code as well. Change-Id: I0421d35657823215229f84231896b84167f90548 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anson Huang authored
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 28 Feb, 2019 4 commits
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John Tsichritzis authored
Due to the shared Mbed TLS heap optimisation introduced in 6d01a463 , common code files were depending on Mbed TLS specific headers. This dependency is now removed by moving the default, unoptimised heap implementation inside the Mbed TLS specific files. Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Antonio Nino Diaz authored
Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Ambroise Vincent authored
Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Chandni Cherukuri authored
Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and 'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product names Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 27 Feb, 2019 4 commits
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Varun Wadekar authored
This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Antonio Nino Diaz authored
This feature is only supported on FVP. Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Chandni Cherukuri authored
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with 'rde1edge' as per the updated product names. Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with 'rdn1edge' as per the updated product names. Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 26 Feb, 2019 2 commits
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Ying-Chun Liu (PaulLiu) authored
This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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- 22 Feb, 2019 1 commit
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Chris Spencer authored
For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow the kernel to use the CAAM job rings. This patch sets the master ID of the Cortex A in the JRaMID registers. Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
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- 20 Feb, 2019 1 commit
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Yann Gautier authored
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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