Skip to content

GitLab

Switch branch/tag
  1. 05 Mar, 2018 1 commit
  3. 29 Jan, 2018 1 commit
  5. 24 Jan, 2018 1 commit
  7. 20 Dec, 2017 1 commit
  9. 06 Dec, 2017 1 commit
  11. 01 Dec, 2017 1 commit
  13. 29 Sep, 2017 1 commit
  15. 01 Sep, 2017 1 commit
  17. 14 Jul, 2017 1 commit
    • Jorge Ramirez-Ortiz's avatar
      Poplar: Initial commit for Poplar E-96Boards · e35d0edb
      Jorge Ramirez-Ortiz authored 
      The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of running any commercial set-top solution based on
Linux or Android. Its high performance specification also supports a
premium user experience with up to H.265 HEVC decoding of 4K video at
60 frames per second.

SOC  Hisilicon Hi3798CV200
CPU  Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB  Two USB 2.0 ports One USB 3.0 ports
CONSOLE  USB-micro port for console support
ETHERNET  1 GBe Ethernet
PCIE  One PCIe 2.0 interfaces
JTAG  8-Pin JTAG
EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI  802.11AC 2*2 with Bluetooth
CONNECTORS  One connector for Smart Card One connector for TSI

The platform boot sequence is as follows:
    l-loader --> arm_trusted_firmware --> u-boot

Repositories:
 - https://github.com/Linaro/poplar-l-loader.git
 - https://github.com/Linaro/poplar-u-boot.git



U-Boot is also upstream in the project's master branch.

Make sure you are using the correct branch on each one of these
repositories. The definition of "correct" might change over time (at
this moment in time this would be the "latest" branch).

Build Line:
make CROSS_COMPILE=aarch64-linux-gnu-  all fip SPD=none DEBUG=1
PLAT=poplar BL33=/path/to/u-boot.bin
Signed-off-by: default avatarJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Tested-by: default avatarJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: default avatarLeo Yan <leo.yan@linaro.org>
Tested-by: default avatarAlex Elder <elder@linaro.org>
      e35d0edb
  19. 12 Jul, 2017 4 commits
  21. 29 Jun, 2017 3 commits
  23. 12 Jun, 2017 2 commits
  25. 07 Jun, 2017 1 commit
  27. 24 May, 2017 1 commit
  29. 28 Feb, 2017 1 commit
  31. 22 Feb, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra: init normal/crash console for platforms · e1084216
      Varun Wadekar authored 
      

The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e1084216
    • Varun Wadekar's avatar
      Tegra: add tzdram_base to plat_params_from_bl2 struct · e0d4158c
      Varun Wadekar authored 
      

This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.

Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e0d4158c
  33. 06 Feb, 2017 1 commit
  35. 15 Jun, 2016 1 commit
  37. 09 Jun, 2016 1 commit
  39. 25 Apr, 2016 2 commits
    • Michal Simek's avatar
      zynqmp: FSBL->ATF handover · b96f77c6
      Michal Simek authored 
      

Parse the parameter structure the FSBL populates, to populate the bl32
and bl33 image structures.

Cc: Sarat Chand Savitala <saratcha@xilinx.com>
Cc: petalinux-dev@xilinx.com
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
[ SB
 - pass pointers to structs instead of structs
 - handle execution state parameter
 - populate bl32 SPSR
 - add documentation
 - query bootmode and consider missing handoff parameters an error when
   not in JTAG boot mode
]
Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
      b96f77c6
    • Soren Brinkmann's avatar
      zynqmp: Revise memory configuration options · 01555332
      Soren Brinkmann authored 
      

Drop the current configuration options for selecting the location of
the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION).
The new configuration provides one default setup (ATF in OCM,
BL32 in DRAM). Additionally, the new configuration options
 - ZYNQMP_ATF_MEM_BASE
 - ZYNQMP_ATF_MEM_SIZE
 - ZYNQMP_BL32_MEM_BASE
 - ZYNQMP_BL32_MEM_SIZE
can be used to freely configure the memory locations used for ATF and
secure payload.

Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE.

Cc: petalinux-dev@xilinx.com
Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
      01555332
  41. 06 Apr, 2016 1 commit
  43. 01 Aug, 2015 1 commit
  45. 31 Jul, 2015 1 commit
  47. 24 Jul, 2015 2 commits
    • Varun Wadekar's avatar
      tlkd: delete 'NEED_BL32' build variable · 458c3c13
      Varun Wadekar authored 
      

Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_BL32 flag does not influence the TLK load/boot
sequence at all. Moreover, it expects that TLK binary be present on
the host before we can compile BL31 support for Tegra.

This patch removes the flag from the makefile and thus decouples both
the build systems.

Tested by booting TLK without the NEED_BL32 flag.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      458c3c13
    • Varun Wadekar's avatar
      Tegra: Support for Tegra's T132 platforms · e7d4caa2
      Varun Wadekar authored 
      

This patch implements support for T132 (Denver CPU) based Tegra
platforms.

The following features have been added:

* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e7d4caa2
  49. 06 Jul, 2015 1 commit
  51. 11 Jun, 2015 1 commit
    • Varun Wadekar's avatar
      Boot Trusted OS' on Tegra SoCs · dc7fdad2
      Varun Wadekar authored 
      

This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.

The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dc7fdad2
  53. 29 May, 2015 1 commit
    • Varun Wadekar's avatar
      Support for NVIDIA's Tegra T210 SoCs · 08438e24
      Varun Wadekar authored 
      

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08438e24