1. 30 Nov, 2020 1 commit
  2. 12 Nov, 2020 2 commits
  3. 09 Oct, 2020 1 commit
  4. 07 Oct, 2020 1 commit
  5. 05 Oct, 2020 2 commits
  6. 28 Sep, 2020 1 commit
  7. 25 Sep, 2020 2 commits
  8. 02 Sep, 2020 1 commit
    • Pramod Kumar's avatar
      lib: cpu: Check SCU presence in DSU before accessing DSU registers · 942013e1
      Pramod Kumar authored
      
      
      The DSU contains system control registers in the SCU and L3 logic to
      control the functionality of the cluster. If "DIRECT CONNECT" L3
      memory system variant is used, there won't be any L3 cache,
      snoop filter, and SCU logic present hence no system control register
      will be present. Hence check SCU presence before accessing DSU register
      for DSU_936184 errata.
      Signed-off-by: default avatarPramod Kumar <pramod.kumar@broadcom.com>
      Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
      942013e1
  9. 31 Aug, 2020 1 commit
  10. 09 Aug, 2020 1 commit
  11. 23 Jul, 2020 1 commit
  12. 25 Jun, 2020 2 commits
  13. 22 Jun, 2020 2 commits
  14. 01 Jun, 2020 2 commits
  15. 02 Apr, 2020 1 commit
    • Masahiro Yamada's avatar
      Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS · 9cefb4b1
      Masahiro Yamada authored
      Commit d5e97a1d ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3
      globally for C files") does not have commit 848a7e8c ("Build:
      introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because
      they were pulled almost at the same time.
      
      This is a follow-up conversion to be consistent with commit
      11a3c5ee
      
       ("plat: pass -D option to BL*_CPPFLAGS instead of
      BL*_CFLAGS").
      
      With this change, the command line option, IMAGE_AT_EL3, will be
      passed to .S files as well.
      
      I remove the definition in include/lib/cpus/aarch64/cpu_macros.S
      
      Otherwise, the following error would happen.
      
        include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]
      
      Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      9cefb4b1
  16. 19 Mar, 2020 1 commit
  17. 20 Feb, 2020 1 commit
    • Varun Wadekar's avatar
      cpus: higher performance non-cacheable load forwarding · cd0ea184
      Varun Wadekar authored
      
      
      The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
      non-cacheable streaming enhancement. Platforms can set this bit only
      if their memory system meets the requirement that cache line fill
      requests from the Cortex-A57 processor are atomic.
      
      This patch adds support to enable higher performance non-cacheable load
      forwarding for such platforms. Platforms must enable this support by
      setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
      makefiles. This flag is disabled by default.
      
      Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      cd0ea184
  18. 18 Feb, 2020 2 commits
  19. 27 Jan, 2020 1 commit
  20. 23 Dec, 2019 2 commits
  21. 11 Oct, 2019 1 commit
  22. 04 Oct, 2019 1 commit
    • laurenw-arm's avatar
      Neoverse N1 Errata Workaround 1542419 · 80942622
      laurenw-arm authored
      
      
      Coherent I-cache is causing a prefetch violation where when the core
      executes an instruction that has recently been modified, the core might
      fetch a stale instruction which violates the ordering of instruction
      fetches.
      
      The workaround includes an instruction sequence to implementation
      defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
      handler to execute a TLB inner-shareable invalidation to an arbitrary
      address followed by a DSB.
      Signed-off-by: default avatarLauren Wehrmeister <lauren.wehrmeister@arm.com>
      Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
      80942622
  23. 03 Oct, 2019 1 commit
  24. 02 Oct, 2019 1 commit
  25. 30 Sep, 2019 1 commit
  26. 10 Sep, 2019 1 commit
  27. 01 Aug, 2019 1 commit
    • Julius Werner's avatar
      Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ · d5dfdeb6
      Julius Werner authored
      
      
      NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
      
      All common C compilers predefine a macro called __ASSEMBLER__ when
      preprocessing a .S file. There is no reason for TF-A to define it's own
      __ASSEMBLY__ macro for this purpose instead. To unify code with the
      export headers (which use __ASSEMBLER__ to avoid one extra dependency),
      let's deprecate __ASSEMBLY__ and switch the code base over to the
      predefined standard.
      
      Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      d5dfdeb6
  28. 31 Jul, 2019 1 commit
  29. 16 Jul, 2019 1 commit
  30. 10 Jul, 2019 1 commit
  31. 02 Jul, 2019 2 commits