- 19 Jun, 2018 6 commits
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Nishanth Menon authored
Do proper initialization of GIC V3. This will allow CP15 access to GIC from "normal world" (aka HLOS) via mrc/mcr calls. K3 SoC family uses GICv3 compliant GIC500 without compatibility for legacy GICv2. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Benjamin Fair <b-fair@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
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Nishanth Menon authored
Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC clock is selected statically and override option if the platform has a different configuration. Signed-off-by:
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Nishanth Menon authored
Signed-off-by:
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Nishanth Menon authored
This library will be used to properly set up mappings from different bootloaders at different exception levels. It ensures that memory mapped devices such as UARTs are still accessible and memory regions have the correct access permissions. Signed-off-by:
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Benjamin Fair authored
Because there is no BL2, BL31 must determine the entrypoint and memory location of BL32 and BL33 on its own. BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board makefile. We also allow a DTB address to be specified for cases when BL33 is a Linux image. NOTE: It is possible to pull in this information from device tree as well, however libfdt does not contain the required hooks to make this happen at this point in time. Signed-off-by:
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Nishanth Menon authored
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by:
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