- 05 Feb, 2019 1 commit
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Thomas Abraham authored
Add a second maintainer for Arm's SGI and SGM platform support in trusted firmware to handle the review and maintenance of existing and upcoming platforms. Change-Id: Ie7fa8da280d9351f7543122fb261d6ac6c7e15ad Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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- 31 Jan, 2019 1 commit
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Ying-Chun Liu (PaulLiu) authored
This patch adds myself to co-maintainer list of Raspberry Pi 3 platform. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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- 14 Jan, 2019 1 commit
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Jacky Bai authored
This patch adds me to various maintainer activities in the ATF tree associated with the NXP i.MX8M platform. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Change-Id: Idd5a2b700b936b22e94194dfadee68b968d03380 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Dec, 2018 1 commit
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Julius Werner authored
I wrote most of this code and have a vested interest in keeping it healthy, so adding myself as a maintainer. Change-Id: I0edeebbc8336b6976dfaf393b3cfc7bc94089ac6 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: Ie2465c1ccc482bd8eb5e5a71c580543095e4ba94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Oct, 2018 1 commit
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Konstantin Porotchkin authored
Move doimage utility from toos/doimage to tools/marvell/doimage. This is done for supporting mode Marvell tools in the future. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 17 Oct, 2018 1 commit
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Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
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- 07 Oct, 2018 1 commit
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Konstantin Porotchkin authored
Declate Marvell's ownership on tools/doimage Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 03 Oct, 2018 1 commit
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Nariman Poushin authored
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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- 07 Sep, 2018 1 commit
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Icenowy Zheng authored
Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller core, with inverted clear quirk. Add a glue driver for this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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- 04 Sep, 2018 1 commit
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Bryan O'Donoghue authored
This patch adds me to various maintainer activities in the ATF tree associated with the NXP i.MX7 generally and WaARP7 in particular. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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- 29 Aug, 2018 1 commit
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Nariman Poushin authored
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- 28 Aug, 2018 1 commit
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Yann Gautier authored
Folders drivers/st/ and include/drivers/st/ are added in maintainers.rst, under STM32MP1 platform port. This will allow notifications for the files modified there. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 10 Aug, 2018 1 commit
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Haojian Zhuang authored
Remove emmc framework from maintain list. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 24 Jul, 2018 1 commit
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 18 Jul, 2018 1 commit
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Konstantin Porotchkin authored
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 04 Jul, 2018 1 commit
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Andre Przywara authored
A proper link to Samuel's github page was missing. Add this to make the link actually work. Change-Id: I68b116935bf045df60b2e9309b5fd58a1c694d47 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Jun, 2018 2 commits
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Andre Przywara authored
As Samuel contributed most of the original code and he has an interest in that, add him as a second maintainer for the Allwinner port. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Antonio Nino Diaz authored
The previous format was not very practical and hard to parse by scripts. The current format is easier as it uses more tokens that can be identified by scripts, while maintaining a reasonably good result when it is rendered. Some maintainers maintain more than one subsystem but they were all part of the same entry. In cases like this the entry has been split into two to clarify what file belongs to which subsystem. The list of maintainers of the Trusted Firmware has been updated. Change-Id: I4be2d527c5171e8d2d86fb49e45e1d9dbcbd2d80 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Jun, 2018 1 commit
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Masahiro Yamada authored
Socionext has multiple product lines. The UniPhier is not the only platform any more. Correct the maintainership. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 21 Jun, 2018 1 commit
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Sumit Garg authored
Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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- 19 Jun, 2018 2 commits
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Nishanth Menon authored
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
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Anson Huang authored
NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and system controller (Cortex-M4) inside, documentation can be found in below link: https://www.nxp.com/products/processors-and-microcontrollers/ applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES This patch adds support for booting up SMP linux kernel (v4.9). Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 15 Jun, 2018 1 commit
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Samuel Holland authored
The Allwinner A64 SoC is quite popular on single board computers. It comes with four Cortex-A53 cores in a singe cluster and the usual peripherals for set-top box/tablet SoC. The ATF platform target is called "sun50i_a64". [Andre: adapted to amended directory layout, removed unneeded definitions ] Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 10 Apr, 2018 1 commit
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Jiafei Pan authored
This patch introduce TF-A support for NXP's ls1043a platform. more details information of ls1043a chip and ls1043ardb board can be found at docs/plat/ls1043a.rst. Boot sequence on ls1043a is: bootrom loads bl1 firstly, then bl1 loads bl2, bl2 will load bl31, bl32 and bl33, bl31 will boot bl32(tee os) and bl33(u-boot or uefi), bl33 boot Linux kernel. Now TF-A on ls1043ardb platform has the following features in this patch: * Support boot from Nor flash. * TF-A can boot bl33 which runs in el2 of non-secure world. * TF-A boot OPTee OS. * Support PSCI Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Chenyin.Ha <Chenyin.Ha@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com> Signed-off-by: Wen He <wen.he_1@nxp.com>
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- 15 Mar, 2018 1 commit
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Dan Handley authored
Update Arm Trusted Firmware references in the upstream documents to Trusted Firmware-A (TF-A). This is for consistency with and disambiguation from Trusted Firmware-M (TF-M). Also update other Arm trademarks, e.g. ARM->Arm, ARMv8->Armv8-A. Change-Id: I8bb0e18af29c6744eeea2dc6c08f2c10b20ede22 Signed-off-by: Dan Handley <dan.handley@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
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- 07 Feb, 2018 1 commit
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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- 06 Dec, 2017 1 commit
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Dan Handley authored
* Update the RockChip sub-maintainer from rkchrome to rockchip-linux in maintainers.rst. * Add missing documentation files and change extensions from `md` to `rst`. * Add sub-maintainer for Socionext UniPhier platform. Change-Id: I7f498316acb0f7947c6432dbe14988e61a8903fe Co-Authored-By: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Dan Handley <dan.handley@arm.com>
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- 01 Dec, 2017 1 commit
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Antonio Nino Diaz authored
This port can be compiled to boot an AArch64 or AArch32 payload with the build option `RPI3_BL33_AARCH32`. Note: This is not a secure port of the Trusted Firmware. This port is only meant to be a reference implementation to experiment with an inexpensive board in real hardware. Change-Id: Ide58114299289bf765ef1366199eb05c46f81903 Co-authored-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 30 Nov, 2017 1 commit
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Siva Durga Prasad Paladugu authored
This patch updates Xilinx maintainers details as sorenb is no more the maintainer for xilinx and the email id is invalid now. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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- 08 Nov, 2017 1 commit
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Etienne Carriere authored
External build environment shall sets directive ARM_ARCH_MAJOR to 7 to specify a target ARMv7-A core. As ARM-TF expects AARCH to be set, ARM_ARCH_MAJOR==7 mandates AARCH=aarch32. The toolchain target architecture/cpu is delegated after the platform configuration is parsed. Platform shall define target core through ARM_CORTEX_A<x>=yes, <x> being 5, 7, 9, 12, 15 and/or 17. Platform can bypass ARM_CORTEX_A<x>=yes directive and provide straight the toolchain target directive through MARCH32_DIRECTIVE. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 29 Jun, 2017 1 commit
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Douglas Raillard authored
Due to recent issues in the rendering of the documentation on GitHub and some long-standing issues like the lack of automatic table of content in Markdown, the documentation has been converted to reStructuredText. Basic constructs looks pretty similar to Markdown. Automatically convert GitHub markdown documentation to reStructuredText using pandoc. Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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