- 10 Oct, 2018 1 commit
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John Tsichritzis authored
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3". Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 03 Oct, 2018 4 commits
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Daniel Boulby authored
Map the initialization code for BL31 to overlap with the memory required for the secondary cores stack. Once BL31 has been initialized the memory can be remapped to RW data so that it can be used for secondary cores stacks. By moving code from .text to .text.init the size of the BL31 image is decreased by a page. Split arm_common.ld.S into two linker scripts, one for tzc_dram (arm_tzc_dram.ld.S) and one for reclaiming initialization code (arm_reclaim_init.ld.S) so that platforms can chose which memory regions they wish to include. Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Daniel Boulby authored
Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Daniel Boulby authored
Mark the initialization functions found in the BL31 boot sequence as __init so they can be reclaimed when no longer needed. Change-Id: I687a89346419c7710ef5097feaa325d83c527697 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Daniel Boulby authored
Remove ARM_MAP_BL_ROMLIB memory region macro as it is now split into two regions for code and data Change-Id: Ic17b5b584933c196db29fe83051d7e0a8e92911c Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 02 Oct, 2018 1 commit
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Antonio Nino Diaz authored
This option makes it hard to optimize the memory definitions of all Arm platforms because any change in the common defines must work in all of them. The best thing to do is to remove it and move the definition to each platform's header. FVP, SGI and SGM were using the definitions in board_arm_def.h. The definitions have been copied to each platform's platform_def.h. Juno was already using the ones in platform_def.h, so there have been no changes. Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 3 commits
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Antonio Nino Diaz authored
- Remove references to removed build options. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I296385ef2ebf829446c76a54400d73f963ed265f Tested-by: Nariman Poushin <nariman.poushin@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
- Remove references to removed build options. - Remove support for legacy GIC driver. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I72f8c05620bdf4a682765e6e53e2c04ca749a3d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Dimitris Papastamos authored
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- 26 Sep, 2018 1 commit
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John Tsichritzis authored
Fixed a Coverity defect by adding a runtime check to avoid potential NULL pointer dereference. Change-Id: I9a0aa0efd27334131ac835b43348658b436c657d Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 24 Sep, 2018 1 commit
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Elieva Pignat authored
For sgm775 the SCP_BL2 build in debug mode is around 94KiB which is higher than the maximum size for SCP_BL2. This patch increase the maximum allowed size for SCP_BL2 to 96KiB. Change-Id: Ibca0daadba41429301c651ae21cbba87e45ccddf Signed-off-by: Elieva Pignat <Elieva.Pignat@arm.com>
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- 21 Sep, 2018 2 commits
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Daniel Boulby authored
Set MULTI_CONSOLE_API=1 for both AArch64 and AArch32 by default. MULTI_CONSOLE_API=0 is still supported, but it has to be set from the command line. Change-Id: I4eeaa8e243a3fe93ed8a716e502666a26ad28f35 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Daniel Boulby authored
Allow AArch32 to use the multi console driver by adding the required functions Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 18 Sep, 2018 1 commit
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Soby Mathew authored
The patch d323af9e removed the support for coherent memory in BL1 and BL2 for ARM platforms. But the CryptoCell SBROM integration depends on use of coherent buffers for passing data from the AP CPU to the CryptoCell. Hence this patch reintroduces support for coherent memory in BL1 and BL2 if ARM_CRYPTOCELL_INTEG=1. Change-Id: I011482dda7f7a3ec9e3e79bfb3f4fa03796f7e02 Signed-Off-by: Soby Mathew <soby.mathew@arm.com>
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- 10 Sep, 2018 1 commit
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Soby Mathew authored
This patch fixes an array overrun in CSS scmi driver if the system power domain level is less than 2. This was reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 308492 Change-Id: I3a59c700490816718d20c71141281f19b2b7e7f7 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 07 Sep, 2018 5 commits
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Sathees Balya authored
The patch 7b56928a unified the FWU mechanism on FVP and Juno platforms due to issues with MCC firmware not preserving the NVFLAGS. With MCCv150 firmware, this issue is resolved. Also writing to the NOR flash while executing from the same flash in Bypass mode had some stability issues. Hence, since the MCC firmware issue is resolved, this patch reverts to the NVFLAGS mechanism to detect FWU. Also, with the introduction of SDS (Shared Data Structure) by the SCP, the reset syndrome needs to queried from the appropriate SDS field. Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554 Signed-off-by: Sathees Balya <sathees.balya@arm.com> Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
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Alexei Fedorov authored
Adds an undocumented build option that enables non-secure access to the PL011 UART1. This allows a custom build where the UART can be used as a serial debug port for WinDbg (or other debugger) connection. This option is not documented in the user guide, as it is provided as a convenience for Windows debugging, and not intended for general use. In particular, enabling non-secure access to the UART might allow a denial of service attack! Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
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John Tsichritzis authored
A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we ensure that the heap info written to the DTB always gets written back to memory. Hence, sharing this info with other images is guaranteed. Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
In Mbed TLS shared heap code, an additional sanity check is introduced in BL2. Currently, when BL2 shares heap with BL1, it expects the heap info to be found in the DTB. If for any reason the DTB is missing, BL2 cannot have the heap address and, hence, Mbed TLS cannot proceed. So, BL2 cannot continue executing and it will eventually crash. With this change we ensure that if the DTB is missing BL2 will panic() instead of having an unpredictable crash. Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
This patch, firstly, makes the error messages consistent to how printed strings are usually formatted. Secondly, it removes an unnecessary #if directive. Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 04 Sep, 2018 3 commits
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John Tsichritzis authored
Change-Id: Ibbfedb6601feff51dfb82c1d94850716c5a36d24 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
Change-Id: Iac454c745543842bfeed004aee7a3f4fb94d37e1 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
This patch introduces the shared Mbed TLS heap optimisation for Arm platforms. The objective is the Mbed TLS heap to be shared between BL1 and BL2 so as to not allocate the heap memory twice. To achieve that, the patch introduces all the necessary helpers for implementing this optimisation. It also applies it for FVP. Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 30 Aug, 2018 2 commits
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Daniel Boulby authored
Add another level of abstraction of weak defs for arm_bl2_handle_post_image_load to prevent two weak definitions of the same function Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Antonio Nino Diaz authored
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Aug, 2018 1 commit
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John Tsichritzis authored
Small patch which removes some redundant casts to (void *). Change-Id: If1cfd68f2989bac1d39dbb3d1c31d4119badbc21 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Aug, 2018 1 commit
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Roberto Vargas authored
All the arm platforms were including the files related to mem-protect. This configuration generates some problems with new platforms that don't support such functionality, and for that reason this patch moves these files to the platform specific makefiles. Change-Id: I6923e5224668b76667795d8e11723cede7979b1e Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 20 Aug, 2018 1 commit
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Jeenu Viswambharan authored
These changes address most of the required MISRA rules. In the process, some from generic code is also fixed. No functional changes. Change-Id: I707dbec9b34b802397e99da2f5ae738165d6feba Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 10 Aug, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I1bb310e1b05968d30b28913c4011c0601e1ae64e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Aug, 2018 1 commit
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Roberto Vargas authored
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 03 Aug, 2018 7 commits
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Nariman Poushin authored
Add support for System Guidance for Mobile platform SGM775 Change-Id: I2442a50caae8f597e5e5949cd48f695cf75d9653 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Deepak Pandey authored
In css platforms where the cpu/cluster management is done by the hardware, software does need to issue certain scmi requests. This patch wraps those scmi calls around the HW_ASSISTED_COHERENCY build option to remove them on platforms that have this hardware support. Change-Id: Ie818e234484ef18549aa7f977aef5c3f0fc26c27 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Nariman Poushin authored
This omission causes a build error as the definition for arm_tzc_regions_info_t is needed from plat_arm.h Change-Id: I26935ee90d3e36ab6a016ff2c4eee4413df3e4e8 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Nariman Poushin authored
Change-Id: I278d6876508800abff7aa2480910306a24de5378 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Chandni Cherukuri authored
The Arm SGI platforms can switch to using SCMI. So enable support for SCMI and remove portions of code that would be unused after switching to SCMI. Change-Id: Ifd9e1c944745f703da5f970b5daf1be2b07ed14e Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it for hotplug and idle to function correctly. The reset value of this bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN in the platform specific reset handler function. Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Roberto Vargas authored
TF Makefile was linking all the objects files generated for the fdt library instead of creating a static library that could be used in the linking stage. Change-Id: If3705bba188ec39e1fbf2322a7f2a9a941e1b90d Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 01 Aug, 2018 1 commit
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Daniel Boulby authored
TF won't build since no memory region is specified for when SEPARATE_CODE_AND_RODATA=0 it still relies on the ARM_MAP_BL_RO_DATA region which is never defined for this case. Create memory region combining code and RO data for when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 26 Jul, 2018 1 commit
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Sughosh Ganu authored
Add the various flags that are required to build the components needed to enable the RAS feature on SGI575 platform. By default, all flags are set to 0, disabling building of all corresponding components. Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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