- 30 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 16 Mar, 2020 3 commits
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Igor Opaniuk authored
Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A53 is enabled). Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled. Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96
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Igor Opaniuk authored
This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Usage: $ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5
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Igor Opaniuk authored
This fixes shift overflow errors, when compiled with CONSOLE_DEBUG support: plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=] Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 05 Mar, 2020 2 commits
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Igor Opaniuk authored
Some boards (f.e. Verdin i.MX8M Mini) use different UART base address for serial debug output, so make this value configurable (as a build option). Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52
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Andre Przywara authored
Since commit ac71344e we have the UART base address in the generic console_t structure. For most platforms the platform-specific struct console is gone, so we *must* use the embedded base address, since there is no storage behind the generic console_t anymore. Replace the usage of CONSOLE_T_DRVDATA with CONSOLE_T_BASE to fix this. Change-Id: I6d2ab0bc2c845c71f98b9dd64d89eef3252f4591 Reported-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 12 Feb, 2020 1 commit
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Jacky Bai authored
Each memory region slot occupies 16bypte space, so correct the the offset of config register address. Change-Id: Ief8f21bb8ada78b5663768ee1e40f9e0eae57165 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 04 Dec, 2019 2 commits
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Samuel Holland authored
This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
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Samuel Holland authored
This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
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- 06 Nov, 2019 1 commit
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Jacky Bai authored
Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 05 Nov, 2019 1 commit
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Jacky Bai authored
Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 24 Jul, 2019 1 commit
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Jacky Bai authored
Add the basic support for RDC init/config driver, this module driver can be enhanced more if necessary. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8
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- 17 Jul, 2019 2 commits
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Jun Nie authored
The PicoPi iMX7D is a 2 board development board consisting of a System-on-Module and a carrier baseboard and optimized for the Internet-of-Things (IoT). This patch add basic support to this board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
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Jun Nie authored
For the iMX7 SOCs, part of the code for platform setup implementation can be reused and made common for all these SoCs. This patch extracts the common part for reuse. Signed-off-by: Jun Nie <jun.nie@linaro.org> Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
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- 12 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 04 Jul, 2019 1 commit
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Jacky Bai authored
CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 01 Jul, 2019 1 commit
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Soby Mathew authored
Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
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- 28 Jun, 2019 2 commits
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Ambroise Vincent authored
Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 21 May, 2019 1 commit
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Jacky Bai authored
AIPSTZ provide access control for all the peripherals connected to it. In this patch all the perperals are configured accessible to all the master. it can be customized based the actual use case. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a
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- 20 May, 2019 2 commits
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Leonard Crestez authored
Platform defines are already provided by the build system so let's not duplicate them. Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Leonard Crestez authored
The manual documents that 0x3036006c should contains the soc revision for imx8mq but this always reports A0. Work around this by parsing the ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa. Determining this inside TF-A makes life easier for OS, see for example this linux discussion: https://lkml.org/lkml/2019/5/3/465 The soc revision can also be useful inside TF-A itself, for example for the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas. The clock for OCOTP block can be disabled by OS so only initialize soc revision once at boot time. Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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- 13 May, 2019 1 commit
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Jacky Bai authored
Remove duplicated linker symbols, resue the symbols defined in bl_common.h Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 09 May, 2019 1 commit
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Leonard Crestez authored
The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but it's also applicable to imx8m. This fixes U-Boot not printing commit hash on 8m with upstream TF-A. Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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- 08 May, 2019 2 commits
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Leonard Crestez authored
Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible by 32. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I286b925eead89218cfeddd82f53a634f3447d212
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Leonard Crestez authored
This is similar to imx8mm and allows uboot to run fastboot over USB otg. There is a different set of power domains on 8mq but same bits covers all off them. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d
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- 12 Apr, 2019 1 commit
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 08 Apr, 2019 1 commit
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Jacky Bai authored
The 'drivers/console/aarch64/console.S' is not needed, so remove it from build to fix the build error when 'ERROR_DEPRECATED'set. Change-Id: Id047a355f82fd33298b7e2b49eff289d28eb5b56 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 03 Apr, 2019 2 commits
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Ambroise Vincent authored
Now it is needed to use the full path of the common header files. Commit 09d40e0e ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The old version of the macro is deprecated. Commit cc5859ca ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 13 Mar, 2019 1 commit
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Jacky Bai authored
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 12 Mar, 2019 1 commit
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Jacky Bai authored
for the i.MX8M SOCs, part of the code for gpc and PSCI implementation can be reused and make it common for all these SoCs. this patch extracts the common part for reuse. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 01 Mar, 2019 1 commit
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Anson Huang authored
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 22 Feb, 2019 1 commit
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Chris Spencer authored
For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow the kernel to use the CAAM job rings. This patch sets the master ID of the Cortex A in the JRaMID registers. Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
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