- 30 Mar, 2020 1 commit
-
-
Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 10 Mar, 2020 1 commit
-
-
Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 25 Feb, 2020 1 commit
-
-
Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
- 07 Feb, 2020 1 commit
-
-
Aditya Angadi authored
In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
-
- 28 Jan, 2020 1 commit
-
-
Louis Mayencourt authored
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
-
- 24 Jan, 2020 1 commit
-
-
Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d
-
- 20 Dec, 2019 2 commits
-
-
Paul Beesley authored
Before adding any new SPM-related components we should first do some cleanup around the existing SPM-MM implementation. The aim is to make sure that any SPM-MM components have names that clearly indicate that they are MM-related. Otherwise, when adding new SPM code, it could quickly become confusing as it would be unclear to which component the code belongs. The secure_partition.h header is a clear example of this, as the name is generic so it could easily apply to any SPM-related code, when it is in fact SPM-MM specific. This patch renames the file and the two structures defined within it, and then modifies any references in files that use the header. Change-Id: I44bd95fab774c358178b3e81262a16da500fda26 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
Paul Beesley authored
There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
- 12 Jul, 2019 1 commit
-
-
Madhukar Pappireddy authored
Fix the header file path Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
-
- 28 Jun, 2019 1 commit
-
-
Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
-
- 13 Mar, 2019 2 commits
-
-
Masahisa Kojima authored
MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
-
Masahisa Kojima authored
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
-
- 22 Jan, 2019 1 commit
-
-
Antonio Nino Diaz authored
The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
-
- 15 Jan, 2019 2 commits
-
-
Ard Biesheuvel authored
Enable the deprecated SPM framework for the SynQuacer platform. It involves creating a memory layout in secure DRAM, and wiring up the SPM infrastructure so that the secure partition payload that is loaded into this region by the SCP firmware is dispatched appropriately. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
Ard Biesheuvel authored
The logic that initializes the BL32 entry point data structure should only be executed if we are in fact loading OP-TEE, and not if BL32_BASE is set for other reasons (i.e., when enabling SPM) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
- 04 Jan, 2019 1 commit
-
-
Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 08 Nov, 2018 1 commit
-
-
Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 28 Sep, 2018 1 commit
-
-
Antonio Nino Diaz authored
- Remove references to removed build options. - Update Makefile paths. - Migrate to bl31_early_platform_setup2(). Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1 Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 30 Aug, 2018 1 commit
-
-
Antonio Nino Diaz authored
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 22 Aug, 2018 1 commit
-
-
Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 24 Jul, 2018 1 commit
-
-
Sumit Garg authored
OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
-
- 20 Jul, 2018 1 commit
-
-
Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 21 Jun, 2018 14 commits
-
-
Sumit Garg authored
Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
Sumit Garg authored
PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Ard Biesheuvel authored
Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-
Sumit Garg authored
synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
-