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This fixes ARM-software/tf-issues#9

Change-Id: Id57037115b8762efc9eaf5ff41887b71d6494c5d

New phony Makefile targets have been added:

 * checkcodebase
 * checkpatch

The checkcodebase target will run a Linux style compliance check over the
entire codebase, and honours the V=1 Makefile verbose setting and so will
show more information when this is enabled.

If the local directory is a git checkout then the output of git ls-files is
used to decide which files to test for compliance.  If the local directory
is not under git control then a 'best attempt' is made, but in this case it
should be noted that it is possible for additional non-codebase files to be
tested, so care should be taken when parsing the output.

The checkpatch target will compare local changes against the git origin/master
to allow issues with the last set of changes to be identified.  To override
the change comparision location, set the BASE_COMMIT variable to your
desired git branch.

Both targets rely on the Linux source tree script checkpatch.pl to do the
syntax checking, and expects that the CHECKPATCH environment variable points
to the location of this file.

Notes on the usage of these targets have been added to the contributing.md
and docs/user-guide.md text files.

Change-Id: I6d73c97af578e24a34226d972afadab9d30f1d8d

Move all explicit platform or architecture specific references
into a new platform.mk file that is defined for each platform.

Change-Id: I9d6320d1ba957e0cc8d9b316b3578132331fa428
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Traps when accessing architectural features are disabled by clearing bits
in CPTR_EL3 during early boot, including accesses to floating point
registers. The value of this register was previously undetermined, causing
unwanted traps to EL3. Future EL3 code (for example, context save/restore
code) may use floating point registers, although they are not used by current
code.

Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to
prevent generation of code that uses floating point registers.

Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747

Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60

This patch makes changes to the documents to reflect the current
state of play of the psci cpu_suspend function.

Change-Id: I086509fb75111b6e9f93b7f6dbcd33cc4591b9f3

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5

This patch updates the user guide section about the memory layout.
  - Explain the verifications that the linker scripts does on the
    global memory layout.
  - Refer to the new linker symbols.
  - Describe the linker symbols exported to the trusted firmware code.

Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286

A single binary can be compiled using a command such as:
  make CROSS_COMPILE=aarch64-none-elf- bl1

Also make use of brackets consistent in the Makefile.

Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e

- Large RAM-disks may have trouble starting with 2GB of memory.
- Increase from 2GB to 4GB in FDT.

Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7

Any asynchronous exception caused by the firmware should be handled
in the firmware itself.  For this reason, unmask SError exceptions
(and Debug ones as well) on all boot paths.  Also route external
abort and SError interrupts to EL3, otherwise they will target EL1.

Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092

Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16

Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66