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  1. 21 Sep, 2020 1 commit
  3. 14 Sep, 2020 1 commit
  5. 14 Aug, 2020 1 commit
  7. 16 Jul, 2020 1 commit
    • Etienne Carriere's avatar
      stm32mp1: SCMI clock and reset service in SP_MIN · fdaaaeb4
      Etienne Carriere authored 
      

This change implements platform services for stm32mp1 to expose clock
and reset controllers over SCMI clock and reset domain protocols
in sp_min firmware.

Requests execution use a fastcall SMC context using a SiP function ID.
The setup allows the create SCMI channels by assigning a specific
SiP SMC function ID for each channel/agent identifier defined. In this
change, stm32mp1 exposes a single channel and hence expects single
agent at a time.

The input payload in copied in secure memory before the message
in passed through the SCMI server drivers. BL32/sp_min is invoked
for a single SCMI message processing and always returns with a
synchronous response message passed back to the caller agent.

This change fixes and updates STM32_COMMON_SIP_NUM_CALLS that was
previously wrongly set 4 whereas only 1 SiP SMC function ID was to
be counted. STM32_COMMON_SIP_NUM_CALLS is now set to 3 since the
2 added SiP SMC function IDs for SCMI services.

Change-Id: Icb428775856b9aec00538172aea4cf11e609b033
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      fdaaaeb4
  9. 08 Jul, 2020 6 commits
  11. 23 Jun, 2020 8 commits
    • Etienne Carriere's avatar
      stm32mp1: SP_MIN embeds Arm Architecture services · 450e15a7
      Etienne Carriere authored 
      

Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This
service is needed by Linux kernel to setup the SMCCC conduit
used by its SCMI SMC transport driver.

Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      450e15a7
    • Etienne Carriere's avatar
      stm32mp1: use last page of SYSRAM as SCMI shared memory · 0754143a
      Etienne Carriere authored 
      

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device) mainly to conform to existing support in
the Linux kernel. Note that executive messages are mostly short
(few 32bit words) hence not using cache will not penalize much
performances.

Platform stm32mp1 shall configure ETZPC to harden properly the
secure and non-secure areas of the SYSRAM address space, that before
CPU accesses the shared memory when mapped non-secure.

This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and
STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE.

Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      0754143a
    • Etienne Carriere's avatar
      stm32mp1: check stronger the secondary CPU entry point · 98641993
      Etienne Carriere authored 
      

When using SP_min as monitor, only sp_min_warm_entrypoint() is a valid
secure entry point.

Change-Id: I440cec798e901b11a34dd482c33b2e378a8328ab
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
Signed-off-by: default avatarNicolas Toromanoff <nicolas.toromanoff@st.com>
      98641993
    • Etienne Carriere's avatar
      stm32mp1: disable neon in sp_min · e4ee1ab9
      Etienne Carriere authored 
      

Disable use of Neon VFP support for platform stm32mp1 when
building with SP_MIN runtime services as these can conflict with
non-secure world use of NEON support. This is preferred over a
systematic backup/restore of NEON context when switching
between non-secure and secure worlds.

When NEON support is disabled, this is done for both BL2 and BL32 as
build process uses common libraries built once for both binaries.

Change-Id: I4e8808dcb6ef58fc839e6f85fd6e45cfbaa34be0
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      e4ee1ab9
    • Etienne Carriere's avatar
      stm32mp1: shared resources: apply registered configuration · 5f038ac6
      Etienne Carriere authored 
      

BL32/SP_MIN configures platform security hardening from the shared
resources driver.  At the end of SP_MIN initialization, all shared
resources shall be assigned to secure or non-secure world by
drivers. A lock prevent from further change on the resource
assignation. By definition, resources not registered are assign
to non-secure world since not claimed by any component on the BL.

No functional change as all resources are currently in state
SHRES_UNREGISTERED hence assigned to non-secure world as prior
this change in stm32mp1_etzpc_early_setup() and
sp_min_platform_setup().

Change-Id: Ic41fab47216c3b8b7a6a75b8358cfcec411ed941
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      5f038ac6
    • Etienne Carriere's avatar
      stm32mp1: shared resources: count GPIOZ bank pins · 722999e3
      Etienne Carriere authored 
      

Get number of pins in the GPIOZ bank with helper function
fdt_get_gpio_bank_pin_count(). Save the value in RAM to prevent
parsing the FDT several time for the same information.

Change-Id: Ie68e300804461ffce09914100a7d2962116023b5
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      722999e3
    • Etienne Carriere's avatar
      stm32mp1: shared resources: define resource identifiers · eafe0eb0
      Etienne Carriere authored 
      

Define enum stm32mp_shres for platform stm32mp1. The enumerated
type defines all resources that can be assigned to secure or
non-secure worlds at run time for the platform.

Change-Id: I5de20d72735856645f1efd0993643278e8d35bcb
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      eafe0eb0
    • Etienne Carriere's avatar
      stm32mp1: introduce shared resources support · 47cf5d3f
      Etienne Carriere authored 
      

STM32MP1 SoC includes peripheral interfaces that can be assigned to
the secure world, or that can be opened to the non-secure world.

This change introduces the basics of a driver that manages such
resources which assignation is done at run time. It currently offers
API functions that state whether a service exposed to non-secure
world has permission to access a targeted clock or reset controller.

Change-Id: Iff20028f41586bc501085488c03546ffe31046d8
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      47cf5d3f
  13. 03 Jun, 2020 1 commit
  15. 01 Jun, 2020 1 commit
    • Etienne Carriere's avatar
      drivers: stm32_reset adapt interface to timeout argument · 45c70e68
      Etienne Carriere authored 
      

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      45c70e68
  17. 11 May, 2020 2 commits
  19. 28 Apr, 2020 1 commit
    • Andre Przywara's avatar
      plat/stm32: Use generic fdt_read_uint32_array() implementation · 52a616b4
      Andre Przywara authored 
      

The device tree parsing code for the STM32 platform is using its own FDT
helper functions, some of them being rather generic.
In particular the existing fdt_read_uint32_array() implementation is now
almost identical to the new generic code in fdt_wrappers.c, so we can
remove the ST specific version and adjust the existing callers.

Compared to the original ST implementation the new version takes a
pointer to the DTB as the first argument, and also swaps the order of
the number of cells and the pointer.

Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      52a616b4
  21. 26 Mar, 2020 4 commits
    • Yann Gautier's avatar
      stm32mp1: use stm32mp_get_ddr_ns_size() function · 5813e6ed
      Yann Gautier authored 
      

Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.

Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      5813e6ed
    • Yann Gautier's avatar
      stm32mp1: set XN attribute for some areas in BL2 · 9c52e69f
      Yann Gautier authored 
      

DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.

Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      9c52e69f
    • Yann Gautier's avatar
      stm32mp1: dynamically map DDR later and non-cacheable during its test · 84686ba3
      Yann Gautier authored 
      

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      84686ba3
    • Yann Gautier's avatar
      stm32mp1: add a function to get non-secure DDR size · e6cc3ccf
      Yann Gautier authored 
      

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.

Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      e6cc3ccf
  23. 25 Feb, 2020 6 commits
  25. 28 Jan, 2020 1 commit
    • Madhukar Pappireddy's avatar
      Enable -Wredundant-decls warning check · ca661a00
      Madhukar Pappireddy authored 
      

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      ca661a00
  27. 24 Jan, 2020 1 commit
  29. 20 Jan, 2020 5 commits