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  1. 14 Jul, 2017 3 commits
  3. 12 Jul, 2017 5 commits
  5. 11 Jul, 2017 1 commit
  7. 10 Jul, 2017 1 commit
  9. 05 Jul, 2017 1 commit
  11. 02 Jul, 2017 1 commit
  13. 30 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume · c3710ee7
      Caesar Wang authored 
      

This patch fixes the two things as follows:

1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".

2) fixes the warnings log.
We always hit the warnings thing during the suspend, as below log:
..
[   51.022334] CPU5: shutdown
[   51.025069] psci: CPU5 killed.
INFO:    sdram_params->ddr_freq = 928000000
WARNING: rk3399_flash_l2_b:reg 28830380,wait

When the L2 completes the clean and invalidate sequence, it asserts the
L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
the L2 deasserts L2FLUSHDONE.

Then, a loop without a delay isn't really great to measure time. We should
probably add a udelay(10) or so in there and then maybe replace the WARN()
after the loop. In the actual tests, the L2 cache will take ~4ms by
default for big cluster.

In the real world that give 10ms for the enough margin, like the
ddr/cpu/cci frequency and other factors that will affect it.

Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      c3710ee7
  15. 28 Jun, 2017 3 commits
    • Soby Mathew's avatar
      Use CryptoCell to set/get NVcounters and ROTPK · f143cafe
      Soby Mathew authored 
      

This patch implements the platform APIs plat_get_rotpk_info,
plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM
APIs when ARM_CRYPTOCELL_INT is set.

Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      f143cafe
    • Soby Mathew's avatar
      ARM plat changes to enable CryptoCell integration · e60f2af9
      Soby Mathew authored 
      

This patch makes the necessary changes to enable ARM platform to
successfully integrate CryptoCell during Trusted Board Boot. The
changes are as follows:

* A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select
  the CryptoCell crypto driver for Trusted Board boot.

* The TrustZone filter settings for Non Secure DRAM is modified
  to allow CryptoCell to read this memory. This is required to
  authenticate BL33 which is loaded into the Non Secure DDR.

* The CSS platforms are modified to use coherent stacks in BL1 and BL2
  when CryptoCell crypto is selected. This is because CryptoCell makes
  use of DMA to transfer data and the CryptoCell SBROM library allocates
  buffers on the stack during signature/hash verification.

Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      e60f2af9
    • Caesar Wang's avatar
      rockchip: enable A53's erratum 855873 for rk3399 · dea1e8ee
      Caesar Wang authored 
      

For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't
support WriteEvict. and you will hit the condition L2ACTLR[3] with 0,
as the Evict transactions should propagate to CCI-500 since it has
snoop filters.

Maybe this erratum applies to all Cortex-A53 cores so far, especially
if RK3399's A53 is a r0p4. we should enable it to avoid data corruption,

Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      dea1e8ee
  17. 27 Jun, 2017 1 commit
    • David Cunado's avatar
      Resolve signed-unsigned comparison issues · 0dd41951
      David Cunado authored 
      A recent commit 030567e6

 added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / errors in the TF static analysis.

This patch addresses these issues by migrating impacted variables from
signed ints to unsigned ints and vice verse where applicable.

Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53
Signed-off-by: default avatarDavid Cunado <david.cunado@arm.com>
      0dd41951
  19. 26 Jun, 2017 3 commits
  21. 23 Jun, 2017 1 commit
  23. 22 Jun, 2017 2 commits
    • Douglas Raillard's avatar
      Apply workarounds for A53 Cat A Errata 835769 and 843419 · a94cc374
      Douglas Raillard authored 
      These errata are only applicable to AArch64 state. See the errata notice
for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html



Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419.
Enable both of them for Juno.

Apply the 835769 workaround as following:
* Compile with -mfix-cortex-a53-835769
* Link with --fix-cortex-a53-835769

Apply the 843419 workaround as following:
* Link with --fix-cortex-a53-843419

The erratum 843419 workaround can lead the linker to create new sections
suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the
linker to create new "*.stub" sections with no particular alignment.

Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for
architecture-specific linker options.

Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8
Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      a94cc374
    • dp-arm's avatar
      aarch64: Enable Statistical Profiling Extensions for lower ELs · d832aee9
      dp-arm authored 
      

SPE is only supported in non-secure state.  Accesses to SPE specific
registers from SEL1 will trap to EL3.  During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained.  This is to
avoid a potential invalid memory access in SEL1.

SPE is architecturally specified only for AArch64.

Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: default avatardp-arm <dimitris.papastamos@arm.com>
      d832aee9
  25. 20 Jun, 2017 5 commits
    • Masahiro Yamada's avatar
      uniphier: embed ROTPK hash into BL1/BL2 · 63634800
      Masahiro Yamada authored 
      

Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info().
It is up to users how to retrieve ROTPK if the ROT verification is
desired.  This is not nice.

This commit improves plat_get_rotpk_info() implementation and automates
the ROTPK deployment.  UniPhier platform has no ROTPK storage, so it
should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case.
This makes sense because UniPhier platform implements its internal ROM
i.e. BL1 is used as updatable pseudo ROM.

Things work like this:

- ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing.
  Users can override ROT_KEY from the command line if they want to
  use a specific ROT key.

- ROTPK_HASH is generated based on ROT_KEY.

- ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2.

- ROT_KEY is input to cert_create tool.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      63634800
    • Dimitris Papastamos's avatar
      juno: Fix AArch32 build · c9711432
      Dimitris Papastamos authored 
      Commit 6de8b24f

 broke Juno AArch32
build.

Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701
Signed-off-by: default avatarDimitris Papastamos <dimitris.papastamos@arm.com>
      c9711432
    • Dimitris Papastamos's avatar
      sp_min: Implement `sp_min_plat_runtime_setup()` · 21568304
      Dimitris Papastamos authored 
      

On ARM platforms before exiting from SP_MIN ensure that
the default console is switched to the runtime serial port.

Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b
Signed-off-by: default avatarDimitris Papastamos <dimitris.papastamos@arm.com>
      21568304
    • David Cunado's avatar
      Resolve build errors flagged by GCC 6.2 · 568ac1f7
      David Cunado authored 
      

With GCC 6.2 compiler, more C undefined behaviour is being flagged as
warnings, which result in build errors in ARM TF build.

This patch addresses issue caused by enums with values that exceed
maximum value for an int. For these cases the enum is converted to
a set of defines.

Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d
Signed-off-by: default avatarDavid Cunado <david.cunado@arm.com>
      568ac1f7
    • David Cunado's avatar
      hikey960: migrate to use A53 specific defines · 0d5eb656
      David Cunado authored 
      The patch fb7d32e5

 migrated the CPU
libraries to have unique defines, prefixing them with the CPU name.

This patch migrates the hikey960 platform port to use the A53 specific
defines.

Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021
Signed-off-by: default avatarDavid Cunado <david.cunado@arm.com>
      0d5eb656
  27. 19 Jun, 2017 1 commit
    • Leo Yan's avatar
      plat: Hikey960: fix the CPU hotplug · 0aedca71
      Leo Yan authored 
      

In CPU off callback function, the old code uses the function
hisi_test_pwrdn_allcores() to check if all CPUs in cluster have been
powered off and if it's valid then power off the whole cluster. But the
function hisi_test_pwrdn_allcores() only maintains the different power
states only for CPU suspend/resume flow, so it cannot return correct
states for CPU on/off flow.

This patch is to change use hisi_test_cpu_down() to check if all CPUs
have been powered off, so that can power off the whole cluster properly
when all CPUs in cluster have been hotplugged off.
Signed-off-by: default avatarTao Wang <kevin.wangtao@hisilicon.com>
Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
      0aedca71
  29. 15 Jun, 2017 11 commits