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  1. 01 Apr, 2020 1 commit
  3. 19 Mar, 2020 1 commit
  5. 25 Feb, 2020 3 commits
  7. 20 Feb, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
  9. 23 Jan, 2020 5 commits
  11. 17 Jan, 2020 2 commits
  13. 28 Nov, 2019 8 commits
    • Varun Wadekar's avatar
      Tegra: introduce plat_enable_console() · 117dbe6c
      Varun Wadekar authored 
      

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      117dbe6c
    • Dilan Lee's avatar
      Tegra194: mce: enable strict checking · ac252f95
      Dilan Lee authored 
      

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: default avatarDilan Lee <dilee@nvidia.com>
      ac252f95
    • Varun Wadekar's avatar
      Tegra194: cleanup references to Tegra186 · 1c62509e
      Varun Wadekar authored 
      

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1c62509e
    • Steven Kao's avatar
      Tegra194: rename secure scratch register macros · 192fd367
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect
their usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*

Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      192fd367
    • Anthony Zhou's avatar
      Tegra194: fix defects flagged by MISRA scan · b6533b56
      Anthony Zhou authored 
      

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      b6533b56
    • Varun Wadekar's avatar
      Tegra194: memctrl: platform handlers to reprogram MSS · f32e8525
      Varun Wadekar authored 
      

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: default avatarPuneet Saxena <puneets@nvidia.com>
Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f32e8525
    • Varun Wadekar's avatar
      Tegra194: core and cluster count values · 1e6a7f91
      Varun Wadekar authored 
      

This patch updates the total number of CPU clusters and number
of cores per cluster, in the platform makefile.

Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1e6a7f91
    • Ajay Gupta's avatar
      Tegra194: program stream ids for XUSB · bc019041
      Ajay Gupta authored 
      

T194 XUSB has support for XUSB virtualization. It will have one
physical function (PF) and four Virtual function (VF)

There were below two SIDs for XUSB until T186.
1) #define TEGRA_SID_XUSB_HOST    0x1bU
2) #define TEGRA_SID_XUSB_DEV    0x1cU

We have below four new SIDs added for VF(s)
3) #define TEGRA_SID_XUSB_VF0    0x5dU
4) #define TEGRA_SID_XUSB_VF1    0x5eU
5) #define TEGRA_SID_XUSB_VF2    0x5fU
6) #define TEGRA_SID_XUSB_VF3    0x60U

When virtualization is enabled then we have to disable SID override
and program above SIDs in below newly added SID registers in XUSB
PADCTL MMIO space. These registers are TZ protected and so need to
be done in ATF.
a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)

This change disables SID override and programs XUSB SIDs in
above registers to support both virtualization and non-virtualization.

Change-Id: I38213a72999e933c44c5392441f91034d3b47a39
Signed-off-by: default avatarAjay Gupta <ajayg@nvidia.com>
      bc019041
  15. 13 Nov, 2019 2 commits
  17. 24 Oct, 2019 2 commits
  19. 05 Feb, 2019 1 commit
  21. 31 Jan, 2019 1 commit
  23. 23 Jan, 2019 2 commits
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Anthony Zhou's avatar
      Tegra186: setup: Fix MISRA Rule 8.4 violation · ad67f8c5
      Anthony Zhou authored 
      

MISRA Rule 8.4, A compatible declaration shall be visible when an
object or function with external linkage is defined.

This patch adds static for local array to fix this defect.

Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      ad67f8c5
  25. 16 Jan, 2019 3 commits
  27. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  29. 18 Dec, 2018 1 commit
  31. 28 Sep, 2018 1 commit
  33. 17 Feb, 2018 1 commit
    • Andreas Färber's avatar
      tegra: Fix mmap_region_t struct mismatch · 28db3e96
      Andreas Färber authored 
      Commit fdb1964c

 ("xlat: Introduce
MAP_REGION2() macro") added a granularity field to mmap_region_t.

Tegra platforms were using the v2 xlat_tables implementation in
common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c
where arrays are being defined. This caused the next physical address to
be read as granularity, causing EINVAL error and triggering an assert.

Consistently use xlat_tables_v2.h header to avoid this.

Fixes ARM-software/tf-issues#548.
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      28db3e96
  35. 14 Jun, 2017 1 commit
  37. 03 May, 2017 1 commit
  39. 13 Apr, 2017 1 commit
  41. 07 Apr, 2017 1 commit