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  1. 24 Aug, 2017 3 commits
  3. 23 Aug, 2017 2 commits
    • Isla Mitchell's avatar
      FVP: Always assume shifted affinity with MT bit · 8431635b
      Isla Mitchell authored 
      

At present, the MPIDR validation on FVP relies on MT bit set along
with shifted affinities. This currently is additionally dependent
on the FVP model being of variant C. This however should be based
on the presence of MT bit alone.

This patch makes the change to always assume that the affinities
are shifted in the FVP model when MT bit is present.

Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d
Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      8431635b
    • Roberto Vargas's avatar
      norflash: Add full status check · 3bbe34e5
      Roberto Vargas authored 
      

The nor_XXXXX functions may fail due to different reasons, and it
is convenient to do a full check to detect any failure. It is also
a good idea to have a specific function to do a full status check,
because new checks can be added to this function and they will be
incorporated automatically to any function calling it.

Change-Id: I54fed913e37ef574c1608e94139a519426348d12
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      3bbe34e5
  5. 22 Aug, 2017 4 commits
  7. 17 Aug, 2017 1 commit
    • Tao Wang's avatar
      Hikey960: fix PSCI suspend stuck issue · 4af7fcb8
      Tao Wang authored 
      

Clear the cpuidle flag when resuming from idle. This flag is set
when entering idle, and if it remains set when resuming, it can
prevent the cluster from powering off during the next system
suspend operation. During system suspend, all CPUs are plugged
out except the last CPU, which is suspended. If any of the
cpuidle flags are set at this point, the last CPU will be stuck
in a WFI loop and will not be powered off.
This problem only occurs during system suspend.
Signed-off-by: default avatarTao Wang <kevin.wangtao@linaro.org>
      4af7fcb8
  9. 16 Aug, 2017 1 commit
    • Fu Wei's avatar
      qemu: Add LOAD_IMAGE_V2 support · 64b31125
      Fu Wei authored 
      

The generic LOAD_IMAGE_V2 framework has been merged and enable for almost
all the arm platform. Because qemu platform doesn't share those common
files with arm, QEMU haven't got this support yet.

This patch add all the necessary code the files for adding LOAD_IMAGE_V2
support on QEMU and enable it as default.

Fixes ARM-software/tf-issues#507
Signed-off-by: default avatarFu Wei <fu.wei@linaro.org>
      64b31125
  11. 15 Aug, 2017 1 commit
    • Julius Werner's avatar
      Add new alignment parameter to func assembler macro · 64726e6d
      Julius Werner authored 
      

Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:

    .align X
  myfunction:

However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.

An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:

  [...]
  endfunc plat_crash_console_putc

  .align 16
  func platform_cpu_warmboot
  [...]

This assembles into the following plat_helpers.o:

  Sections:
  Idx Name                             Size  [...]  Algn
   9 .text.plat_crash_console_putc 00010000  [...]  2**16
  10 .text.platform_cpu_warmboot   00000080  [...]  2**3

As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).

There's no real way to fix this with the existing func macro. Code like

 func myfunc
 .align X

happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.

Also fix up all existing instances of this dangerous antipattern.

Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      64726e6d
  13. 09 Aug, 2017 2 commits
    • Summer Qin's avatar
      Add Trusted OS extra image parsing support for ARM standard platforms · 54661cd2
      Summer Qin authored 
      

Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to 3 images
for optee os: header, pager and paged images. Header image is the info
about optee os and images. Pager image include pager code and data.
Paged image include the paging parts using virtual memory.

Change-Id: Ia3bcfa6d8a3ed7850deb5729654daca7b00be394
Signed-off-by: default avatarSummer Qin <summer.qin@arm.com>
      54661cd2
    • Summer Qin's avatar
      Support Trusted OS firmware extra images in TF tools · 71fb3964
      Summer Qin authored 
      

Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add support
for the new images within the existing Trusted OS firmware
content certificate.

Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06
Signed-off-by: default avatarSummer Qin <summer.qin@arm.com>
      71fb3964
  15. 02 Aug, 2017 1 commit
    • Jeenu Viswambharan's avatar
      FVP: Support Base FVP RevC · 955242d8
      Jeenu Viswambharan authored 
      

Revision C of the Base FVP has the same memory map as earlier revisions,
but has the following differences:

  - Implements CCI550 instead of CCI400,
  - Has a single instantiation of SMMUv3,
  - CPU MPIDs are shifted left by one level, and has MT bit set in them.

The correct interconnect to program is chosen at run time based on the
FVP revision. Therefore, this patch implements FVP functions for
interconnect programming, rather than depending on ARM generic ones. The
macros used have been renamed to reflect this change.

Additionally, this patch initializes SMMUv3 as part of FVP early
platform setup.

New ARM config flags are introduced for feature queries at run time.

Change-Id: Ic7b7f080953a51fceaf62ce7daa6de0573801f09
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      955242d8
  17. 01 Aug, 2017 3 commits
    • Jeenu Viswambharan's avatar
      FVP: Remove CCI registers from crash dump · eeb9ff99
      Jeenu Viswambharan authored 
      

The CCI crash dump macros assumes CCI base at build time. Since this
can't be the case for CCI on FVP, choose not to register dump CCI
registers for FVP.

Change-Id: I7374a037e7fd0a85b138e84b3cf0aa044262da97
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      eeb9ff99
    • Jeenu Viswambharan's avatar
      FVP: Add support for multi-threaded CPUs · 11ad8f20
      Jeenu Viswambharan authored 
      

ARM CPUs with multi-threading implementation has more than one
Processing Element in a single physical CPU. Such an implementation will
reflect the following changes in the MPIDR register:

  - The MT bit set;

  - Affinity levels pertaining to cluster and CPUs occupy one level
    higher than in a single-threaded implementation, and the lowest
    affinity level pertains to hardware threads. MPIDR affinity level
    fields essentially appear shifted to left than otherwise.

The FVP port henceforth assumes that both properties above to be
concomitant on a given FVP platform.

To accommodate for varied MPIDR formats at run time, this patch
re-implements the FVP platform-specific functions that translates MPIDR
values to a linear indices, along with required validation. The same
treatment is applied for GICv3 MPIDR hashing function as well.

An FVP-specific build option FVP_MAX_PE_PER_CPU is introduced which
specifies the maximum number of threads implemented per CPU. For
backwards compatibility, its value defaults to 1.

Change-Id: I729b00d3e121d16ce9a03de4f9db36dfac580e3f
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      11ad8f20
    • Jeenu Viswambharan's avatar
      FVP: Fix AArch32 stack functions to be ABI-compliant · eecdf19b
      Jeenu Viswambharan authored 
      

plat_get_my_stack is called from C, so it can't expect argument
registers to be preserved. Stash registers temporarily onto the stack
instead.

plat_set_my_stack is called during early init, when there exists no
stack. Use any register other than argument registers to stash temporary
values.

Change-Id: I98052e20671d0933201d45ec7a5affccd71ce08c
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      eecdf19b
  19. 31 Jul, 2017 2 commits
  21. 26 Jul, 2017 2 commits
    • Sandrine Bailleux's avatar
      xlat lib v2: Expose *_ctx() APIs · a9ad848c
      Sandrine Bailleux authored 
      

In a previous patch, the xlat_ctx_t type has been made public.
This patch now makes the *_ctx() APIs public.

Each API now has a *_ctx() variant. Most of them were already implemented
and this patch just makes them public. However, some of them were missing
so this patch introduces them.

Now that all these APIs are public, there's no good reason for splitting
them accross 2 files (xlat_tables_internal.c and xlat_tables_common.c).
Therefore, this patch moves all code into xlat_tables_internal.c and
removes xlat_tables_common.c. It removes it from the library's makefile
as well.

This last change introduces a compatibility break for platform ports
that specifically include the xlat_tables_common.c file instead of
including the library's Makefile. The UniPhier platform makefile has
been updated to now omit this file from the list of source files.

The prototype of mmap_add_region_ctx() has been slightly changed. The
mmap_region_t passed in argument needs to be constant because it gets
called from map_add(), which receives a constant region. The former
implementation of mmap_add() used to cast the const qualifier away,
which is not a good practice.

Also remove init_xlation_table(), which was a sub-function of
init_xlat_tables(). Now there's just init_xlat_tables() (and
init_xlat_tables_ctx()). Both names were too similar, which was
confusing. Besides, now that all the code is in a single file,
it's no longer needed to have 2 functions for that.

Change-Id: I4ed88c68e44561c3902fbebb89cb197279c5293b
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      a9ad848c
    • Leo Yan's avatar
      hikey: Disable VBUS_DET interrupt for PMIC · c9e8774c
      Leo Yan authored 
      

After disconnect Jumper pin 1-2 in J15 header, the signal VBUS_DET is to
be pulled down to low level. This will assert the interrupt signal in
PMIC and trigger IRQ in GIC; the asserted signal from VBUS_DET is level
triggered and kernel reports the warning for unhooked interrupt handling;
and VBUS_DET stays with low level, this triggers IRQ storm in kernel.

This patch is to disable interrupt for VBUS_DET in PMIC, this can
dismiss the verbose log and IRQ storm after kernel booting.

[   40.835279] irq 57: nobody cared (try booting with the "irqpoll" option)
[   40.842075] CPU: 0 PID: 980 Comm: irq/57-hi655x-p Not tainted 4.4.77-568944-g576a0114dec8-dirty #667
[   40.851303] Hardware name: HiKey Development Board (DT)
[   40.856580] Call trace:
[   40.859060] [<ffffff800808c4cc>] dump_backtrace+0x0/0x1e0
[   40.864516] [<ffffff800808c8ac>] show_stack+0x20/0x28
[   40.869622] [<ffffff80084b9688>] dump_stack+0xa8/0xe0
[   40.874729] [<ffffff800812dd5c>] __report_bad_irq+0x40/0xec
[   40.880360] [<ffffff800812e0bc>] note_interrupt+0x1e4/0x2d8
[   40.885992] [<ffffff800812b11c>] handle_irq_event_percpu+0xd8/0x268
[   40.892324] [<ffffff800812b2f8>] handle_irq_event+0x4c/0x7c
[   40.897955] [<ffffff800812ecbc>] handle_level_irq+0xcc/0x178
[   40.903672] [<ffffff800812a778>] generic_handle_irq+0x34/0x4c
[   40.909481] [<ffffff80085074c8>] pl061_irq_handler+0xa8/0x124
[   40.915286] [<ffffff800812a778>] generic_handle_irq+0x34/0x4c
[   40.921092] [<ffffff800812a820>] __handle_domain_irq+0x90/0xf8
[   40.926985] [<ffffff8008082620>] gic_handle_irq+0x58/0xa8
Signed-off-by: default avatarDmitry Shmidt <dimitrysh@google.com>
Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
      c9e8774c
  23. 25 Jul, 2017 1 commit
  25. 20 Jul, 2017 3 commits
    • Soby Mathew's avatar
      CSS: Prevent SCP_BL2/2U from overwriting BL1 RW data · 1ea63d77
      Soby Mathew authored 
      

On ARM CSS platforms, the SCP_BL2/2U image is loaded below
BL1 read-write data. This same memory is used to load BL31
later on. But sufficient checks were not done to ensure that the
SCP_BL2 would not overwrite BL1 rw data. This patch adds the
required CASSERT checks to prevent overwrite into BL1 or BL2
memory by load of SCP_BL2/2U. Also the size of BL31 is increased
and SCP_BL2/2U size is decreased to accomodate it within the
allocated region.

Change-Id: I23b28b5e1589e91150852a06452bd52b273216ee
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      1ea63d77
    • Soby Mathew's avatar
      CSS: Reorganize the SCP Image transfer functionality · 74d44a49
      Soby Mathew authored 
      

The SCP_BL2 is transferred to SCP during BL2 image load and authenticate
sequence. The Boot-Over-MHU (BOM) protocol is used as transport for this. After
the SCP boots using the transferred image, the AP CPU waits till the `READY`
message is received from SCP. This patch separates the API for transport of
image from the wait for `READY` message and also moves the related files to
the `css/drivers` folder. The previous API `scp_bootloader_transfer` is
renamed to `css_scp_boot_image_xfer` to reflect the css naming convention.
This reorganisation also allows easier switch to a different transport
(eg: Shared Data Structure based transfer) in future

Change-Id: I8a96f9c4616ffde6dbfdf7c18f6f6f8bfa40bbf0
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      74d44a49
    • Soby Mathew's avatar
      Resize the BL2 size limit for Juno · 6c401f31
      Soby Mathew authored 
      

Recent patches to reduce the memory footprint of BL images have
resulted in saving several pages of memory. This patch reduces
the BL2 size limit by 20KB for Juno when ARM_BOARD_OPTIMISE_MEM=1
so that more free space can be freed up for Trusted OS (BL32). Also
SCP_BL2/SCP_BL2U size is now restricted to 80K.

Change-Id: I1573d7a34e24d15e4abce8a14da40dbb5dc81e37
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      6c401f31
  27. 14 Jul, 2017 3 commits
  29. 12 Jul, 2017 5 commits
  31. 11 Jul, 2017 1 commit
  33. 10 Jul, 2017 1 commit
  35. 05 Jul, 2017 1 commit
  37. 02 Jul, 2017 1 commit
  39. 30 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume · c3710ee7
      Caesar Wang authored 
      

This patch fixes the two things as follows:

1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".

2) fixes the warnings log.
We always hit the warnings thing during the suspend, as below log:
..
[   51.022334] CPU5: shutdown
[   51.025069] psci: CPU5 killed.
INFO:    sdram_params->ddr_freq = 928000000
WARNING: rk3399_flash_l2_b:reg 28830380,wait

When the L2 completes the clean and invalidate sequence, it asserts the
L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
the L2 deasserts L2FLUSHDONE.

Then, a loop without a delay isn't really great to measure time. We should
probably add a udelay(10) or so in there and then maybe replace the WARN()
after the loop. In the actual tests, the L2 cache will take ~4ms by
default for big cluster.

In the real world that give 10ms for the enough margin, like the
ddr/cpu/cci frequency and other factors that will affect it.

Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      c3710ee7
  41. 28 Jun, 2017 1 commit