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  1. 15 Jan, 2020 1 commit
  3. 08 Mar, 2019 1 commit
  5. 04 Jan, 2019 13 commits
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock get parent EEMI API · b6c56bdb
      Jolly Shah authored 
      

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to get pre_src, post_src, div2
and bypasss, in the implementation of pm_clock_get_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
   *_POST_SRC, *_INT_MUX or *_PLL clock IDs); or
2) given clock ID is truly an on-chip clock.
For case 1) we'll map the call onto PLL-specific EEMI API with the
respective parameter ID. For case 2) the call is passed to the PMU.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      b6c56bdb
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock set parent EEMI API · be48511e
      Jolly Shah authored 
      

Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to set pre_src, post_src, div2
and bypass, in the implementation of pm_clock_set_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly
an on-chip clock.
For case 1) we'll map the call onto PLL set parameter EEMI API with the
respective parameter ID. Since clock set parent interface to EL1/2 receives
parent index (mux select value), the value is just passed to PMU.
Functions that appear to be unused after this change is made are removed.

Setting the parent of *PLL clocks, that actually model bypass, is not
possible. This is already ensured by the existing clock model having the
CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the
bypass parent. Bypass is controlled only by the PMU firmware.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      be48511e
    • Jolly Shah's avatar
      zynqmp: pm: Cleanup for clock set/get rate EEMI API · 8bc945fb
      Jolly Shah authored 
      

Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      8bc945fb
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock get divider EEMI API · b071dcd9
      Jolly Shah authored 
      

Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      b071dcd9
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock set divider EEMI API · 48dc44e3
      Jolly Shah authored 
      

Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      48dc44e3
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock get state (status) EEMI API · bd30503a
      Jolly Shah authored 
      

Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux is_enabled method for PLLs still uses clock get state API
get the PLL state, in the implementation of pm_clock_getstate() we need
to workaround this by distinguishing two cases: 1) if the given clock ID
corresponds to a PLL output clock ID; or 2) given clock ID is truly an
on-chip clock whose state of the gate should be returned.
For case 1) we'll call pm_api_clock_pll_getstate() implemented in
pm_api_clock.h/c. This function will query the PLL state from PMU using
the system-level PLL get mode EEMI API.
For case 2) we'll call the PMU to query the clock gate state using
system-level clock get status EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      bd30503a
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock disable EEMI API · d3a78ca4
      Jolly Shah authored 
      

Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock disable API to reset the PLL in the
implementation of pm_clock_disable() we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_disable() implemented in
pm_api_clock.h/c. This function will reset the PLL using the system-level
PLL set mode EEMI API with the reset mode argument.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock disable EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      d3a78ca4
    • Jolly Shah's avatar
      zynqmp: pm: Reimplement clock enable EEMI API · bd642dde
      Jolly Shah authored 
      

Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock enable API to trigger locking of the PLLs
in the pm_clock_enable() implementation we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_enable() implemented in
pm_api_clock.h/c. This function checks what is the buffered PLL mode and
calls the system-level PLL set mode EEMI API with the buffered mode value
specified as argument. Long term, if linux driver get fixed to use PLL
EEMI API to control PLLs, this case could be removed from ATF.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock enable EEMI API.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      bd642dde
    • Jolly Shah's avatar
      zynqmp: pm: Implement PLL get mode EEMI API · 20279793
      Jolly Shah authored 
      

This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      20279793
    • Jolly Shah's avatar
      zynqmp: pm: Implement PLL set mode EEMI API · 5f1a5fee
      Jolly Shah authored 
      

This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target PLL prior to asserting the reset. If integer or
fractional mode is set the PM controller will program and trigger
locking of the PLL. If success status is returned the PLL is locked
and its bypass is deasserted. If fractional mode is set the fractional
divider (data parameter) has to have a non-zero value prior to issuing
pll set fractional mode. The caller need to ensure that the data
parameter is properly set using pll get/set parameter EEMI API.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      5f1a5fee
    • Jolly Shah's avatar
      zynqmp: pm: Implement PLL get parameter EEMI API · d833f64c
      Jolly Shah authored 
      

This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug1087.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      d833f64c
    • Jolly Shah's avatar
      zynqmp: pm: Implement PLL set parameter EEMI API · bfed44a1
      Jolly Shah authored 
      

This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractional mode. Parameter values represent the values as defined
in the Zynq MPSoC register reference manual ug1087.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <WILLW@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
      bfed44a1
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  7. 04 Sep, 2018 2 commits
  9. 27 Aug, 2018 1 commit
    • Rajan Vaja's avatar
      zynqmp: pm: Add API to get number of clocks · ec9712ce
      Rajan Vaja authored 
      

Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clock names by special clock name
string. Add new query data parameter to get actual number of
clocks so Linux can get actual clock numbers in advance.
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
      ec9712ce
  11. 17 May, 2018 10 commits
  13. 15 Mar, 2018 7 commits
  15. 09 Jan, 2018 1 commit
  17. 14 Jul, 2017 1 commit
  19. 03 May, 2017 1 commit
  21. 16 Nov, 2016 2 commits