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Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
appropriate base address, size and attributes.

Example of usage in upcoming commits.

Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

tf_printf and tf_snprintf are now called printf and snprintf, so the
code needs to be updated.

Change-Id: Iffeee97afcd6328c4c2d30830d4923b964682d71
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This allows the console drivers to be implemented in C

Change-Id: Ibac859c4bcef0e92a0dcacc6b58ac19bc69b8342
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

The CCI500 TRM explicitily requires completion of the write
operation before the read operation, and it is not guaranteed
by dmb but it is dsb.

Change-Id: Ieeaa0d1a4b8fcb87108dea9b6de03d9c8a150829
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Because of -Werror, this causes a build error.

Change-Id: I37a8c4bbfe3f2ced5e17981a2814985919ad483b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Replace emmc framework by mmc framework.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Migrate dw_mmc driver from emmc framework to mmc framework. The
emmc framework will be abandoned.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

It should set buswidth and speed of mmc controller before accessing
mmc.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

DMA is always used in mmc driver. So the buffer address should
always follow the DMA limitation.

There're same requirement in mmc_read_blocks()/mmc_write_blocks()
on parameter buf. Since parameter buf comes from io_block driver,
it's already handled in io_block driver.

At here, just make the minimum address alignment on 16 chars.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

mmc_read_blocks()/mmc_write_blocks() derived from io_block_ops_t
type. It means that lba param should be integer type, not
unsigned integer type.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Sending CMD8 before CMD1 just causes to fetch data failure in eMMC.
Check whether it's eMMC first. If it's eMMC, send CMD1 command instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Functions provided by stdio.h such as printf and sprintf are available
in the codebase, but they add a lot of code to the final image if they
are used:

- AArch64: ~4KB
- AArch32: ~2KB in T32, ~3KB in A32

tf_printf and tf_snprintf are a lot more simple, but it is preferable
to use them when possible because they are also used in common code.

Change-Id: Id09fd2b486198fe3d79276e2c27931595b7ba60e
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

We had exit but we didn't have atexit, and we were calling panic and
tf_printf from exit, which generated a dependency from exit to them.
Having atexit allows to set a different function pointer in every image.

Change-Id: I95b9556d680d96249ed3b14da159b6f417da7661
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Mbebtls include paths are controlled by the user using the variable
MBEDTLS_DIR and they are out of the TF source tree. Since these
includes have a different origin it is better to move them to a
different variable.

This change makes easier for the romlib Makefile to parse the include
paths.

Change-Id: I3e4c99300f1012bc7f88c6b9f5bc0ec1f7b5aa8d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

TF Makefile was linking all the objects files generated for the
Mbed TLS library instead of creating a static library that could be
used in the linking stage.

Change-Id: I8e4cd843ef56033c9d3faeee71601d110b7e4c12
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

A new function mmc_reset_to_idle is also created.
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4.

Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.
Signed-off-by: Andrew F. Davis <afd@ti.com>

The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.

STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>

The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write
in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status
register to be sure that the operation is finished before leaving the
functions. If the write in SNOOP_CTRL_REGISTER is reordered after the first
read in the status register then these functions can finish before
enabling/disabling snoops and DVM messages.

The CCI500 TRM specifies:

	Wait for the completion of the write to the Snoop Control Register
	before testing the change_pending bit.

Change-Id: Idc7685963f412be1c16bcd3c6e3cca826e2fdf38
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platforms.

Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/54589

Add i2c driver for A8K SoC family.

Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add COMPHY driver for usage in a runtime service.

Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration

Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810

Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110

Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add address decoding unit drivers for Marvell SoCs.

Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt

Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

This change is largely based on existing eMMC framework by Haojian Zhuang
(@hzhuang1).

The MMC framework supports both eMMC and SD card devices. It was
written as a new framework since breaking few eMMC framework APIs.

At card probe and after the reset to idle command (CMD0), a Send
Interface Condition Command is sent (CMD8) to distinguish between
eMMC and SD card devices. eMMC devices go through the same
sequence as in the former eMMC framework. Else the framework
uses commands dedicated to SD-cards for init or frequency switch.

A structure is created to share info with the driver. It stores:
- the MMC type (eMMC, SD or SD HC)
- the device size
- the max frequency supported by the device
- the block size: 512 for eMMC and SD-HC and read from CSD
 structure for older SD-cards

Restriction to align buffers on block size has been removed.
Cache maintenance was removed and is expected to be done in the platform
or device driver.

The MMC framework includes some MISRA compliance coding style
maybe not yet ported in the existing eMMC framework.

Fixes ARM-software/tf-issues#597
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Platform can define MAX_NUM_FIP_DEVICES in platform_def.h
to define the number of FIP io devices.

The FIP driver doesn't support muliple open file.
So only one single file can be open at a time across
multiple FIP devices.

For any FIP device, an image should be loaded
fully before moving on to the next image.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>

To build with the new release, we pick couple of more files from mbedTLS
library.

Change-Id: I77dfe5723284cb26d4e5c717fb0e6f6dd803cb6b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the future UUIDs that are already generated, but we can store
all the bytes using arrays and modify fiptool to generate the UUIDs with
the correct byte order.

Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Rule 5.1: External identifiers shall be distinct

Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.

Fixed for:
    LOG_LEVEL=50 PLAT=fvp

Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

On TI platforms the UART is disabled by default and must be explicitly
enabled using the MDR1 register.

NOTE: The original definition of
http://www.ti.com/lit/ds/symlink/pc16550d.pdf

 has no MDR register, but
many TI SoCs implementing 16550 do have a quirky MDR register
implemented. So, this should be enabled with TI_16550_MDR_QUIRK

NOTE: In such implementation, the CSR register does not exist.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>