- 21 May, 2019 1 commit
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Yoshifumi Hosoya authored
Update M3 Ver.3.0 QoS setting rev.0.03. Change-Id: I892521d456c606ac3d30f2b2ac6b4e16faa5fc48 Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 14 May, 2019 1 commit
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John Stultz authored
We've seen issues with some THG based UFS chips, where after reset the LUNs don't always enumerate properly. After some debugging, we found that extending the mdelay here seems to resolve the issue by giving the chips enough time to complete reset. Change-Id: I848f810b2438ed6ad3d33db614c61d2cef9ac400 Signed-off-by: John Stultz <john.stultz@linaro.org>
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- 10 May, 2019 1 commit
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Alexei Fedorov authored
For security DMA should be blocked at the SMMU by default unless explicitly enabled for a device. SMMU is disabled after reset with all streams bypassing the SMMU, and abortion of all incoming transactions implements a default deny policy on reset. This patch also moves "bl1_platform_setup()" function from arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and fvp_ve_bl1_setup.c files. Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 03 May, 2019 1 commit
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Alexei Fedorov authored
This patch is a preparation for the subsequent changes in SMMUv3 driver. It introduces a new "smmuv3_poll" function and replaces inline functions for accessing SMMU registers with mmio read/write operations. Also the infinite loop for the poll has been replaced with a counter based timeout. Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 25 Apr, 2019 1 commit
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Heiko Stuebner authored
Rockchip re-uses the ti uart console driver and for aarch32 needs a specific variant, so add it. There are also aarch32 ti socs, so it may be useful for them as well at some point. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17
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- 24 Apr, 2019 1 commit
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Ambroise Vincent authored
It removes the need to unregister the console on system suspend. Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Apr, 2019 1 commit
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Aditya Angadi authored
Add a driver for configuring the SBSA Generic Watchdog which aids in the detection of errant system behaviour. Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 12 Apr, 2019 1 commit
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 11 Apr, 2019 5 commits
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Toshiyuki Ogasahara authored
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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Yoshifumi Hosoya authored
Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode. This patch fixes the DBSC4 self-refresh mode sequence. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com> Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
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Chiaki Fujii authored
[IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
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Yoshifumi Hosoya authored
Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252. [IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver.3.0 QoS setting rev.0.11. - Update M3 Ver.1.1 QoS setting rev.0.19. - Update M3 Ver.3.0 QoS setting rev.0.02. - Update M3N Ver.1.1 QoS setting rev.0.09. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
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Yusuke Goda authored
Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New] Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
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- 09 Apr, 2019 1 commit
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Joel Hutton authored
Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 08 Apr, 2019 2 commits
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Joel Hutton authored
This changes the auth_img_desc_t struct to have pointers to struct arrays instead of struct arrays. This saves memory as many of these were never used, and can be NULL pointers. Note the memory savings are only when these arrays are not initialised, as it is assumed these arrays are fixed length. A possible future optimisation could allow for variable length. memory diff: bl1: bl2: text text -12 -12 bss bss -1463 0 data data -56 -48 rodata rodata -5688 -2592 total total -7419 -2652 Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
When Trusted Board Boot is enabled, we need to specify the Chain of Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array of image descriptors. The authentication module assumes that each image descriptor in this array is indexed by its unique image identifier. For example, the Trusted Boot Firmware Certificate has to be at index [TRUSTED_BOOT_FW_CERT_ID]. Unique image identifiers may not necessarily be consecutive. Also, a given BL image might not use all image descriptors. For example, BL1 does not need any of the descriptors related to BL31. As a result, the CoT array might contain holes, which unnecessarily takes up space in the BL binary. Using pointers to auth_img_desc_t structs (rather than structs themselves) means these unused elements only use 1 pointer worth of space, rather than one struct worth of space. This patch also changes the code which accesses this array to reflect the change to pointers. Image descriptors not needed in BL1 or BL2 respectively are also ifdef'd out in this patch. For example, verifying the BL31 image is the responsibility of BL2 so BL1 does not need any of the data structures describing BL31. memory diff: bl1: bl2: text text -20 -20 bss bss -1463 0 data data -256 -48 rodata rodata -5240 -1952 total total -6979 -2020 Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 03 Apr, 2019 3 commits
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Ambroise Vincent authored
Now it is needed to use the full path of the common header files. Commit 09d40e0e ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Types tzc_action_t and tzc_region_attributes_t are deprecated. Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The old version of the macro is deprecated. Commit cc5859ca ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 02 Apr, 2019 10 commits
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Remi Pommarel authored
In order to configure and boot SCP, BL31 has to compute and send the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC has a DMA facility that could be used to offload SHA-256 computations. This adds basic support of this hardware SHA-256 engine. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Valentine Barshak authored
Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
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Marek Vasut authored
Add QoS tables for R-Car D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add PFC tables for R-Car D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add R-Car D3 DDR initialization code. The code is in staging and needs cleanup, and possibly can even be merged with the E3 init code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add WTCNT register configuration for the D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add SCIF configuration specifics for the D3 SoC, that is detection of the D3 SoC and SCBRR configuration. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The D3 SoC has one CPU core, just return 1 as a CPU number. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add comment into the ROM driver that the new table is also D3 compatible. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 01 Apr, 2019 2 commits
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Ambroise Vincent authored
Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 22 Mar, 2019 1 commit
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Tien Hock, Loh authored
dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC initialization will fail as the initialization treats the device as EMMC instead of SD. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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- 13 Mar, 2019 2 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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Masahisa Kojima authored
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 12 Mar, 2019 3 commits
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Paul Beesley authored
The comment suggests checking version numbers and a checksum but there doesn't seem to be any usable data for either of these. For example, fip_toc_header_t doesn't contain any version information and neither does fip_toc_entry_t. As the function name "is_valid_header" suggests, this function is not concerned with checksumming any of the table of contents entries. Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
This TODO was added five years ago so I assume that there is not going to be a shutdown API added after all. Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Tien Hock, Loh authored
There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is now handled in the dw_prepare function - after the CMD completes, when doing dw_read, we need to invalidate cache and wait for the data transfer to complete - Need to set FIFO threshold, otherwise DMA might never get the interrupt to read or write Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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- 08 Mar, 2019 1 commit
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Yann Gautier authored
STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges 3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field. Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 07 Mar, 2019 1 commit
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Tien Hock, Loh authored
Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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- 04 Mar, 2019 1 commit
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Marek Vasut authored
Configure the GPIO5 09 pin as input on the ULCB board by default, since the pin is routed on the expansion connector and not connected to anything by default. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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