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  1. 28 Apr, 2021 1 commit
    • David Horstmann's avatar
      feat(fdt): introduce wrapper function to read DT UUIDs · d13dbb6f
      David Horstmann authored 
      

TF-A does not have the capability to read UUIDs in string form
from the device tree. This capability is useful for readability,
so add a wrapper function, fdtw_read_uuid() to parse UUIDs from
the DT.
This function should parse a string of the form:

"aabbccdd-eeff-4099-8877-665544332211"

to the byte sequence in memory:

[aa bb cc dd ee ff 40 99 88 77 66 55 44 33 22 11]

Change-Id: I99a92fbeb40f4f4713f3458b36cb3863354d2bdf
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      d13dbb6f
  3. 27 Apr, 2021 1 commit
  5. 26 Apr, 2021 1 commit
    • Chris Kay's avatar
      docs(license): rectify `arm-gic.h` license · 3dbbbca2
      Chris Kay authored 
      

The `arm-gic.h` file distributed by the Linux kernel is disjunctively
dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause
license has been applied in violation of the requirements of both
licenses. This change ensures the file is correctly licensed under the
terms of the MIT license, and that we comply with it by distributing a
copy of the license text.

Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
      3dbbbca2
  7. 21 Apr, 2021 1 commit
    • Alexei Fedorov's avatar
      Plat FVP: Fix Generic Timer interrupt types · dfa6c540
      Alexei Fedorov authored 
      

The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:

Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."

Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."

The following files in fdts\

fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts

describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:

interrupts = <1 13 0xff01>,
             <1 14 0xff01>,
             <1 11 0xff01>,
             <1 10 0xff01>;

, see include\dt-bindings\interrupt-controller\arm-gic.h:

which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware

This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.

Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      dfa6c540
  9. 20 Apr, 2021 3 commits
  11. 14 Apr, 2021 1 commit
  13. 13 Apr, 2021 1 commit
  15. 07 Apr, 2021 1 commit
    • Max Shvetsov's avatar
      Fix: Remove save/restore of EL2 timer registers · a7cf2743
      Max Shvetsov authored 
      

Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
	cnthps_ctl_el2
	cnthps_tval_el2
	cnthps_cval_el2
	cnthvs_ctl_el2
	cnthvs_tval_el2
	cnthvs_cval_el2
	cnthp_ctl_el2
	cnthp_cval_el2
	cnthp_tval_el2
	cnthv_ctl_el2
	cnthv_cval_el2
	cnthv_tval_el2
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
      a7cf2743
  17. 01 Apr, 2021 1 commit
  19. 31 Mar, 2021 1 commit
  21. 26 Mar, 2021 1 commit
    • Bharat Gooty's avatar
      driver: brcm: add i2c driver · 48c6a6b6
      Bharat Gooty authored 
      

Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.
Signed-off-by: default avatarBharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
      48c6a6b6
  23. 24 Mar, 2021 8 commits
  25. 23 Mar, 2021 1 commit
    • Yann Gautier's avatar
      tzc400: add support for interrupts · 34c1a1a4
      Yann Gautier authored 
      

A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.

Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      34c1a1a4
  27. 18 Mar, 2021 2 commits
    • Tomas Pilar's avatar
      tools_share/uuid: Add EFI_GUID representation · e831923f
      Tomas Pilar authored 
      

The UEFI specification details the represenatation
for the EFI_GUID type. Add this representation to the
uuid_helper_t union type so that GUID definitions
can be shared verbatim between UEFI and TF-A header
files.

Change-Id: Ie44ac141f70dd0025e186581d26dce1c1c29fce6
Signed-off-by: default avatarTomas Pilar <tomas@nuviainc.com>
      e831923f
    • Chris Kay's avatar
      arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms · 4e04478a
      Chris Kay authored 
      

The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made
optional in prior extensions, but the checks in our code-base do not
reflect that, assuming that it is only available in Armv8.5-A or later.

This change introduces the `ENABLE_FEAT_SB` definition, which derives
support for the `sb` instruction in the assembler from the feature
flags passed to it. Note that we assume that if this feature is enabled
then all the cores in the system support it - enabling speculation
barriers for only a subset of the cores is unsupported.
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea
      4e04478a
  29. 15 Mar, 2021 1 commit
  31. 10 Mar, 2021 2 commits
  33. 08 Mar, 2021 1 commit
  35. 01 Mar, 2021 1 commit
  37. 25 Feb, 2021 1 commit
  39. 24 Feb, 2021 1 commit
  41. 15 Feb, 2021 1 commit
    • Andre Przywara's avatar
      plat/arm: juno: Condition Juno entropy source with CRC instructions · eb18ce32
      Andre Przywara authored 
      

The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.

To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.

This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.

Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      eb18ce32
  43. 11 Feb, 2021 2 commits
  45. 09 Feb, 2021 1 commit
    • Heyi Guo's avatar
      tzc400: fix logical error in FILTER_BIT definitions · 3d66ca6d
      Heyi Guo authored 
      

The filters parameter passed to tzc400_configure_region() is supposed
to be filter bit flag without bit shift, so the macros
TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL
should always construct the value without any shift.

It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky
to be 0.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5d363c462b8517256523f637e670eefa56722afd
      3d66ca6d
  47. 05 Feb, 2021 1 commit
  49. 04 Feb, 2021 1 commit
  51. 03 Feb, 2021 3 commits