- 28 Nov, 2019 3 commits
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Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
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Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 19 Aug, 2019 1 commit
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Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
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- 15 Aug, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 24 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by:
Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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