Commits · b33772eb9c6e501d33885f7ecd4c6b465cbfad70 · adam.huang / Arm Trusted Firmware

28 Nov, 2019 1 commit

intel: Refactor common platform code [1/5] · 328718f2

Hadi Asyrafi authored Oct 23, 2019



Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d

328718f2

19 Aug, 2019 1 commit

intel: agilex: Clear PLL lostlock bypass mode · 960a12b3

Hadi Asyrafi authored Aug 16, 2019

To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1

960a12b3

14 Aug, 2019 1 commit

intel: agilex: Fix reliance on hard coded clock information · 4e865bd2

Hadi Asyrafi authored Aug 14, 2019

Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133

4e865bd2

17 Jul, 2019 1 commit

intel: Adds support for Agilex platform · 2f11d548

Hadi Asyrafi authored Jun 27, 2019


Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef

2f11d548